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检索条件"主题词=CMOS Logic Circuits"

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Switch-Level Test Calculation for cmos circuits

Switch-Level Test Calculation for CMOS Circuits

引用

International Workshop on Microprocessor Test and Verification (MTV)

作者： József Sziray Department of Informatics Széchenyi University Gyor Hungary

The paper presents a test calculation principle which serves for producing tests of switch-level logic faults in cmos digital circuits. The considered fault model includes stuck-at-0/1 logic faults on the connecting control lines, as well as switch faults in the transistors. Both single and multiple faults are included. The transistor faults manifest themselves in stuck open (open circuit) and stuck short (short circuit) behavior. In this paper only combinational logic is taken into consideration. The computations are performed at the transistor level directly, i. e., by using the original transistor schematic solely, without any logic conversion. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program.

关键词： Circuit testing Switching circuits Circuit faults cmos logic circuits logic testing Switches cmos digital integrated circuits Digital circuits Semiconductor device modeling Joining processes

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Low power high performance keeper technique for high fan-in dynamic gates

Low power high performance keeper technique for high fan-in ...

引用

European Conference on Circuit Theory and Design, ECCTD

作者： Farhad Haj Ali Asgari Majid Ahmadi Jonathan Wu Electrical and Computer Engineering Department University of Windsor Windsor ONT Canada

This paper presents a new technique which combines variable-threshold (VT) keeper with split-domino (SD) logic technique to improve the power performance. The proposed technique yields 9-14% energy reduction, with 10% area overhead. We will compare the proposed method with the-state-of-the art for reducing leakage current in domino logic circuits. A 16-bit multiplexer circuit, in 0.13 mum cmos technology operating at 500 MHz is used as our test-bench.

关键词： logic circuits Circuit noise Leakage current Multiplexing cmos logic circuits Noise reduction Noise level Voltage Circuit testing cmos technology

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A multi gbps 10-pam receiver in 0.18um cmos technology

A multi gbps 10-pam receiver in 0.18um cmos technology

引用

International Symposium on Integrated circuits (ISIC)

作者： Jeongjun Lee Jikyung Jeong Jinwook Burm Department of Electronic Engineering Sogang University Seoul South Korea

We report a receiver for ten-level pulse-amplitude modulated (10-PAM) encoded data signals, which was measured to receive data at 8 Gb/s at a maximum frequency (2 GHz). To increase data bit-rate and reduce BER, we designed this circuit by using a current mode amplifier, high speed comparator and a current-mode logic (CML) circuit. The 10-PAM receiver is designed in 0.18 ¿m cmos technology. The measured current consumption is 61 mA from 1.8-V supply, and the active chip area is 0.5 × 0.6 mm 2 .

关键词： cmos technology Pulse amplifiers Pulse measurements Pulse modulation Frequency measurement Bit error rate cmos logic circuits logic design logic circuits Area measurement

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The Implementation of Single-Phase Power-Gating Adiabatic circuits Using Improved CAL circuits

The Implementation of Single-Phase Power-Gating Adiabatic Ci...

引用

Pacific-Asia Conference on circuits, Communications and Systems, PACCS

作者： Jinghong Fu Jianping Hu Xiaoyan Luo Faculty of Information Science and Technology Ningbo University Ningbo Zhejiang China

This paper focuses on the full-custom layout implementation of the single-phase power-gating adiabatic circuits. A transmission gate is used as the power-gating switch, and the power-gated adiabatic logic block uses the CAL (clocked adiabatic logic) circuits. A power-gating 8-bit full adder based on improved CAL circuits is verified. For a comparison, an 8-bit full adder based on improved CAL circuits without power-gating has also been drawn. All circuits are implemented with TSMC 0.18 um process. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the improved CAL 8-bit full adder with the power-gating scheme can work very well, and it attains more than 36.2% power reductions than the 8-bit full adder without power-gating at 100 MHz when active is 0.2.

关键词： logic circuits Clocks Adders cmos logic circuits Switches Circuit simulation logic devices Power dissipation MOS devices Information science

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Secure Clocked QCA logic for implementation of Quantum Cryptographic Processors

Secure Clocked QCA logic for implementation of Quantum Crypt...

引用

International Conference on Applied Electronics, AE

作者： Ehsan Rahimi Shahram Mohammad Nejad Nanoptronics Research Center Department of Electrical Engineering Iran University of Science and Technology Tehran Iran

Since the introduction of side-channel attacks, cryptographic devices have been highly susceptible to power and electromagnetic analysis attacks; because these attacks require only relatively inexpensive equipments. Unless adequate countermeasures are implemented, side channel attacks allow an unauthorized person to reveal the private key of a cryptographic module. As a new countermeasure a novel logic approach to implement cryptographic processors in, named Secured Clocked Quantum-dot Cellular Automata (SCQCA) logic has been presented. The proposed logic takes advantage of low power consumption Quantum-dot Cellular Automata together with complicated clocking schemes as a paradigm of nanotechnology advances in cryptography engineering.

关键词： Clocks Quantum cellular automata Cryptography Energy consumption cmos logic circuits Electrons Polarization Quantum dots cmos technology logic devices

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A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm cmos

A 5b 800MS/s 2mW asynchronous binary-search ADC in 65nm CMOS

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IEEE International Conference on Solid-State circuits (ISSCC)

作者： Ying-Zu Lin Soon-Jyh Chang Yen-Ting Liu Chun-Cheng Liu Guang-Ying Huang National Cheng-Kung University Tainan Taiwan

This paper reports a 5b asynchronous binary-search ADC with reference-range prediction. The maximum conversion speed of this ADC is 800 MS/s at a cost of 2 mW power consumption. The ADC is fabricated in a 1P6M 65 nm C... 详细信息

关键词： Voltage Energy consumption Clocks logic circuits Flip-flops Electrical resistance measurement Sampling methods Multiplexing Switching converters cmos logic circuits

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Efficient Design of Shift Registers Using Reversible logic

Efficient Design of Shift Registers Using Reversible Logic

引用

International Conference on Signal Processing Systems, ICSPS

作者： Noor Muhammed Nayeem Md. Adnan Hossain Lafifa Jamal Hafiz Md. Hasan Babu Department of Computer Science and Engineering University of Dhaka Dhaka Bangladesh

Reversible shift registers are required to construct reversible memory circuits. This paper presents novel designs of reversible shift registers such as serial-in serial-out (SISO), serial-in parallel-out (SIPO), parallel-in serial-out (PISO), parallel-in parallel-out (PIPO) and universal shift registers. In order to show the efficiency, lower bounds of the proposed designs are shown in terms of number of gates required, garbage outputs produced and quantum cost needed. As far as it is known, this is the first attempt to apply reversible logic to implement shift registers (except SISO). Appropriate theorems and lemmas are presented to clarify the proposed designs. The contribution of this paper will engender a new thread of research in the field of reversible sequential circuits.

关键词： Shift registers logic design Quantum computing Costs Sequential circuits cmos logic circuits logic circuits DH-HEMTs Temperature cmos technology

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Powering embedded cmos logic on MEMS-based micro-robots

Powering embedded CMOS logic on MEMS-based micro-robots

引用

IEEE International Workshop on Behavioral Modeling and Simulation (BMAS)

作者： Jung H. Cho Mark G. Arnold Lehigh University USA

A hypothetical new digital-design paradigm called field programmable robot arrays (FPRAs) has been introduced in which raises a number problems that need to be solved for successful implementation. An FPRA combines cmos reprogrammable logic with micro-robots having constrained motion and sensing capabilities. The goal of the FPRAs is to build digital-logic structures by physical motion as well as the electronic reconfiguration (commonly used in prior programmable logic). In this paper, we present the development of a circuit for powering the digital logic portion of FPRAs. We assume for physical motion the FPRA uses MEMS-based scratch drive actuator (SDA) micro-robots like those developed by Donald et al. as a foundation to build other features needed to develop FPRA. We validate this by developing Verilog-A model of an electrostatic actuator and simulating in Cadence AMS (analog mixed signal) environment.

关键词： cmos logic circuits Actuators Micromechanical devices Robotic assembly Voltage Programmable logic arrays Reconfigurable logic Medical robotics Orbital robotics Sensor arrays

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Subthreshold deep submicron performance investigation of cmos and DTcmos biasing schemes for reconfigurable computing

Subthreshold deep submicron performance investigation of CMO...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： A.K. Kureshi Naushad Alam Mohd. Hasan Tughrul Arslan Department of Electronics Engineering Aligarh Muslim University Aligarh India School of Engineering and Electronics University of Edinburgh Edinburgh UK

ISBN: (纸本)9781424438273

This paper investigates subthreshold cmos logic for ultra low power applications on next generation reconfigurable devices. The performance characteristics of key digital building blocks such as arithmetic units, multiplexers and look-up-tables have been analyzed in terms of speed, power dissipation and power delay product using Berkeley predictive technology models at 22 nm technology node for both the conventional subthreshold cmos (cmos) and the dynamic threshold subthreshold cmos (DTcmos). Simulation results show that DTcmos has lower PDP and sensitivities to process variations compared to cmos for the digital blocks. Moreover, the PDP of blocks can be further improved by using longer channel lengths.

关键词： cmos technology cmos logic circuits logic devices Reconfigurable logic Digital arithmetic Multiplexing Performance analysis Power dissipation Delay Semiconductor device modeling

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Tunelogic: Post-silicon tuning of dual-Vdd designs

TuneLogic: Post-silicon tuning of dual-Vdd designs

引用

IEEE International Symposium on Quality Electronic Design

作者： Stephen Bijansky Sae Kyu Lee Adnan Aziz University of Texas Austin USA

Modern cmos manufacturing processes have significant variability, which necessitates guard banding to achieve reasonable yield. It is our thesis that variability should be addressed post-manufacturing. The fundamental contribution we make is a dual-Vdd design style, and associated CAD algorithms, wherein we assign supply voltages to logic based on post-manufacturing analysis rather than designing with nominal values and guard banding. We perform a detailed case study of a custom designed pipelined multiplier using realistic process data. Our results show that for comparable yield and target delay, we can achieve significantly less power than a single-Vdd supply. For example, to achieve 100% yield at same target delay, Tune-logic uses 23.6 pJ/multiply while a single-Vdd design uses 34.6 pJ/multiply.

关键词： Delay Algorithm design and analysis Design automation logic design Low voltage Web pages Threshold voltage cmos process Manufacturing processes cmos logic circuits

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