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检索条件"主题词=CMOS Logic Circuits"

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An effective approach to detect logic soft errors in digital circuits based on GRAAL

An effective approach to detect logic soft errors in digital...

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IEEE International Symposium on Quality Electronic Design

作者： Hai Yu Michael Nicolaidis Lorena Anghel TIMA Laboratory (CNRS UJF INPG) Grenoble France

Due to the notable change of channel width, supply voltage; and clock frequency, cmos IC technologies are rapidly approaching their ultimate limits. By approaching these limits, circuits are becoming increasingly sensitive to noise, which will result in unacceptable error rates and make further nanometer scaling increasingly difficult. The error detection scheme based on GRAAL architecture (Global Reliability Architecture Approach for logic) combines latch-based design and time redundancy techniques to achieve high detection efficiency for temporary faults (timing faults, SEUs, and SETs) at low area, power and speed penalties. In this paper, we use a finite state machine (FSM) circuit as test vehicle to validate the error detection architecture. The experimental results validate the claimed high error detection efficiency.

关键词： logic circuits Digital circuits cmos logic circuits cmos technology Electrical fault detection Fault detection Circuit faults Circuit testing Voltage Clocks

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Electric power in ballistic devices: A reformulation with full Coulomb interaction

Electric power in ballistic devices: A reformulation with fu...

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Spanish Conference on Electron Devices

作者： G. Albareda A. Alarcon X. Oriols Departament d'Enginyeria Electrònica Universitat Autònoma Barcelona Bellaterra Spain

An accurate formulation of the electric power in ballistic (classical or quantum) nanoscale devices is presented. The redefinition of the electric power is computed within a many-electron framework (where the dynamic of each electron is determined by its own electric field). The traditional definition of the electric power is compared with the new reformulation presented here for classical double-gate MOSFETs. The accurate results with the many-electron approach show not-negligible discrepancies when compared with the standard definition. Such discrepancies become very important when the single-transistor power is extrapolated to the number of transistors in CPUs.

关键词： Electron devices Nanoscale devices MOSFETs Energy consumption Poisson equations Double-gate FETs cmos logic circuits logic devices Mutual coupling Particle scattering

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High speed VLSI implementation of a finite field multiplier using redundant representation

High speed VLSI implementation of a finite field multiplier ...

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European Conference on Circuit Theory and Design, ECCTD

作者： Ashkan Hosseinzadeh Namin Karl Leboeuf Roberto Muscedere Huapeng Wu Majid Ahmadi Department of Electrical and Computer Engineering University of Windsor Windsor ONT Canada

A new VLSI implementation for a 197-bit finite field multiplier using redundant representation is presented. The proposed design uses a simple module designed in domino logic as the main building block for the multiplier. We have used .18 mum cmos technology from TSMC for our design. The final multiplier design was successfully simulated at a clock rate of 1.82 GHz. The proposed multiplier is at least 190% more efficient compared to similar designs, considering the product of area and delay as a measure of performance. Large field size finite field multipliers which operate at high speeds, such as the proposed design, have applications in public key cryptography.

关键词： Very large scale integration Galois fields cmos technology cmos logic circuits logic design Clocks Product design Delay Area measurement Public key cryptography

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A reconfigurable dynamic logic cell for programmable datapaths

A reconfigurable dynamic logic cell for programmable datapat...

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Southeastern Symposium on System Theory

作者： David H. K. Hoe Department of Electrical Engineering University of Technology Tyler USA

A programmable dynamic logic circuit for use in reconfigurable fabrics is described. The proposed circuit is based upon dynamic domino cmos logic. This approach for implementing reconfigurable logic provides added flexibility in programmable datapaths by allowing the implementation of complex logic structures that are not feasible with the configurable logic blocks used in conventional FPGAs. An important application is the acceleration of the critical path found in the carry-chain of a wide-bit adder.

关键词： Reconfigurable logic Programmable logic arrays Field programmable gate arrays cmos logic circuits Table lookup logic circuits Fabrics logic devices Programmable logic devices Clocks

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Selection of Optimum Device Size and Trans-Conductance Ratio for High Speed Digital cmos Inverter Design for a Given Fanout Load

Selection of Optimum Device Size and Trans-Conductance Ratio...

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International Conference on Emerging Trends in Engineering and Technology, ICETET

作者： Abhijit Asati Subhendu Kumar Sahoo Chandra Shekhar Birla Institute of Technology and Science Pilani Rajasthan India Central Electronics Engineering Research Institute Pilani Rajasthan India

The PMOS/NMOS width ratio (ß) and W/L ratio of NMOS device is an important ratio in the design of digital logic cells using conventional cmos logic design style. In this paper we propose a simulation-based method applied to cmos inverter to accurately estimate an optimum W/L ratio of NMOS device and PMOS/NMOS width ratio when fanout loading of 1, 4 and 8 cells of similar type are present. The appropriate selection of W/L ratio of NMOS device and PMOS/NMOS width ratio makes the digital design faster and reduces the power consumption.

关键词： Inverters MOS devices cmos logic circuits logic design logic devices Voltage logic gates Circuit noise cmos technology Energy consumption

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NDR based threshold logic fabric with memristive synapses

NDR based threshold logic fabric with memristive synapses

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IEEE Conference on Nanotechnology

作者： Jeyavijayan Rajendran Harika Manem Garrett S. Rose Department of Electrical and Computer Engineering Polytechnic Institute of New york University Brooklyn NY USA

ISBN: (纸本)9781424448326

In recent years, many researchers have proposed the usage of molecular scale devices exhibiting negative differential resistance (NDR) in the realization of programmable logic circuitry. This paper deals with the utilization of one such system built from NDR based circuitry, specifically the Goto pair, in the implementation of a programmable threshold logic array (PTLA). Furthermore, the PTLA considered here uses memristors exhibiting multiple levels of resistance to provide weighted inputs to each threshold gate. Circuit level considerations for the Goto pair to be implemented as part of PTLA are discussed. An image classification application is also implemented using the proposed PTLA and simulated for functionality and performance using Cadence Spectre.

关键词： Fabrics logic devices Memristors Programmable logic arrays logic circuits cmos logic circuits Diodes Nanoscale devices Boolean functions Programmable logic devices

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Repair techniques for hybrid Nano/cmos computational architecture

Repair techniques for hybrid Nano/CMOS computational archite...

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IEEE Conference on Nanotechnology

作者： Saket Srivastava Aissa Melouki Bashir M. Al-Hashimi School of Electronics and Computer Science University of Southampton Southampton UK

ISBN: (纸本)9781424448326

Presence of high defect rate in nanofabrics due to the inadequate fabrication processes has held back the development of emerging technology architecture. In this work, we propose two repair techniques to provide high level of defect tolerance in lookup table (LUT) based Boolean logic approach implemented in nano/cmos. Further, we demonstrate that direct application of memory repair techniques is ineffective in dealing with high defect rate in hybrid nano/cmos architecture. We show that the proposed techniques are capable of handling more than 20% defect rate in hybrid nano/cmos architecture with efficient utilization of spare units.

关键词： Computer architecture Table lookup cmos technology cmos logic circuits Boolean functions cmos memory circuits Tagging Computer interfaces Error correction codes cmos process

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A novel modular smart PIC technology platform for functional diversification

A novel modular smart PIC technology platform for functional...

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International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： Jun Cai Larry Szendrei David Caron Steven Park Fairchild Semiconductor Corporation South Portland ME USA

Toward great flexibility in making advanced analog interfaces, a novel modular smart PIC technology platform for functional diversification is proposed. This technology platform offers high voltage capability, high current level, very large variety of integrable components, and process modular flexibility thorough diversification or simplification according to the different product application needs. Masks can be added or subtracted based upon product design. A modular route creation system allows us to create the lowest cost process flow for the product needs. Applications of interest for the modular smart PIC technology we focus on ultra-portable, computing, consumer and communication.

关键词： cmos logic circuits cmos process Voltage cmos technology Energy management Product design Thermal management logic devices logic design Isolation technology

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Leakage dissipation reduction of single-phase power-gating adiabatic sequential circuits using MTcmos

Leakage dissipation reduction of single-phase power-gating a...

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Jianping Hu Jinghong Fu Faculty of Information Science and Technology Ningbo University Ningbo Zhejiang China

Reducing leakage dissipation is becoming more and more important in low-power design. The dynamic energy dissipation reduction of adiabatic circuits using power-gating schemes has been introduced. In order to reduce leakage losses of the adiabatic circuits using power-gating schemes under deep submicron process, this paper proposes a MTcmos (Multi-Threshold cmos) power-gating scheme for adiabatic sequential circuits based on two-phase CPAL (complementary pass-transistor adiabatic logic) circuits, which can operate in a single-phase power clock by introducing a two-phase power-clock generator. A practical sequential system with a mode-10 counter is demonstrated using the MTcmos power-gating scheme. All circuits are verified using HSPICE, and BSIM4 model is adopted to reflect the characteristics of the leakage currents. Simulations show that the leakage losses are greatly reduced.

关键词： Sequential circuits cmos logic circuits Energy dissipation cmos process Clocks Power generation Counting circuits Power system modeling Leakage current Circuit simulation

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Design of cmos inverter-based output buffers adapting the cherry-hooper broadbanding technique

Design of CMOS inverter-based output buffers adapting the ch...

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European Conference on Circuit Theory and Design, ECCTD

作者： Tomoaki Maekawa Shuhei Amakawa Noboru Ishihara Kazuya Masu Integrated Research Institute Tokyo Institute of Technology Yokohama Japan

A methodology for designing cmos inverter-based output buffers considering speed, gain, jitter, and drivability requirements is presented. In this methodology, the band-broadening technique of the classic Cherry-Hooper amplifier is adapted for cmos inverters. A buffer designed in this manner offers higher speed than a commonly used simple chain of inverters with exponentially increasing gate widths. The buffer is implemented by making minor modifications to a 4-stage cmos inverter chain. The proposed design is suitable for output buffers for high-speed cmos logic circuits.

关键词： Inverters Design methodology Jitter cmos technology cmos logic circuits Bandwidth Circuit simulation Paper technology Digital integrated circuits Velocity measurement

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