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检索条件"主题词=CMOS Logic Circuits"

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An image combiner and acquisition interface for space remote sensing applications

An image combiner and acquisition interface for space remote...

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Midwest Symposium on circuits and Systems (MWSCAS)

作者： Tsan-Jieh Chen Herming Chiueh Hann-Huei Tsai Chin-Fong Chiu Department of Electrical Engineering National Chiao Tung University Hsinchu Taiwan National Applied Research Laboratories National Chip Implementation Center Hsinchu Taiwan

High resolution image combination and processing plays an important role in today's satellites' remote sensing applications. This paper presents an image recombination and processing circuitries (ICAI) for one-dimensional multi-strip cmos image sensors. The proposed system take advantage of the satellites' linear moving property to control the expose time of cmos image sensor and provides the realtime ability to continuous generate 12,000 times N high-resolution image for space remote sensing applications. The ICAI chip contains an image sensor control logics, image combiner, and host interface, one-dimensional pixel is combined to form a two-dimensional image by proposed circuitry. A prototype chip of ICAI was designed and fabricated with TSMC 0.18 mum cmos 1P6M technology. The die size is 2.91 mm by 2.91 mm, and the power consumption is 20 mW operating at 8 MHz under a 1.8 V supply voltage.

关键词： Remote sensing cmos image sensors Satellites Space technology cmos technology Image resolution Control systems Image sensors cmos logic circuits logic circuits

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0.15µm BiC-DMOS technology with novel stepped-STI N-channel LDMOS

0.15µm BiC-DMOS technology with novel stepped-STI N-channel...

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International Symposium on Power Semiconductor Devices and Ics (ISPSD)

作者： Shinichiro Yanagi H. Kimura T. Nitta T. Kuroi K. Hatasako S. Maegawa K. Onishi Y. Otsu Renesas Technology Corporation Itami Hyogo Japan Renesas Semiconductor Engineering Corp. 4-1 Mizuhara Itami Hyogo 664-0005 Japan

We developed a state-of-the-art BiC-DMOS process using 0.15 mum technology. High-voltage MOSFETs were embedded in our standard 0.15 mum cmos process with a 0.13 mum high density NVM. More intelligent mixed signal devices can flexibly be realized by this technology. Moreover, the reliability of n-ch LDMOS is markedly improved by the novel structure of stepped-STI LDMOS.

关键词： Degradation cmos technology Hot carrier injection Proximity effect Intrusion detection Impact ionization Nonvolatile memory logic devices cmos process cmos logic circuits

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An improved comparison circuit for low power pre-computation-based content-addressable memory designs

An improved comparison circuit for low power pre-computation...

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IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Yu-Ting Pai Chia-Han Lee Shanq-Jang Ruan Edwin Naroska Department of Electronic Engineering National Taiwan University of Science and Technology Taipei Taiwan Department of Mechanical Engineering University of Applied Sciences Ingolstadt Germany

ISBN: (纸本)9781424450909;9781424450916

This paper proposes a cmos comparison architecture for low-power pre-computation-based content-addressable memory (PB-CAM). Instead of conventional architecture, we implement ours by cmos logic gates to eliminate power consumption induced by short-circuit current. We use TSMC 0.18-¿m techfile to estimate the power consumption by Synopsys Nanosim. The width ratio between PMOS and NMOS is set as 3:1. This ratio can effectively reduce both rise time and fall time, thereby reducing the delay for each comparison cycle. Compare with static pseudo-nMOS CAM word circuit, this architecture can save 50.2% power consumption on average.

关键词： Computer aided manufacturing CADCAM Buffer storage Energy consumption MOS devices cmos logic circuits Design engineering Power engineering and energy cmos technology Mechanical engineering

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Switch level optimization of digital cmos gate networks

Switch level optimization of digital CMOS gate networks

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IEEE International Symposium on Quality Electronic Design

作者： Leomar S. da Rosa Felipe R. Schneider Renato P. Ribas Andre I. Reis Departamento de Informe#x00E1 tica UFPel Pelotas Rio Grande do Sul Brazil Nangate Inc. Menlo Park CA USA Instituto de Informe#x00E0 tica UFRGS Porto Alegre Rio Grande do Sul Brazil

This paper presents a comprehensive investigation of how transistor level optimizations can be used to increase design quality of cmos logic gate networks. Different properties of transistor networks are used to explain features and limitations of different methods. We describe which figures of merit, including the logical effort, affect the design quality of cell transistor networks. Further, we compare six different approaches that generate transistor networks, including two with guaranteed theoretical minimum length transistor chains. This comparison shows that minimum length chains reduce the logical effort of the networks.

关键词： Switches cmos logic circuits Bridge circuits Design optimization logic gates Binary decision diagrams Joining processes Catalogs Switching circuits Electronic mail

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Design techniques of P-Type cmos circuits for gate-leakage reduction in deep sub-micron ICs

Design techniques of P-Type CMOS circuits for gate-leakage r...

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Midwest Symposium on circuits and Systems (MWSCAS)

作者： Weiqiang Zhang Linfeng Li Jianping Hu Faculty of Information Science and Technology Ningbo University Ningbo China

With rapid technology scaling, the proportion of the static power catches up with dynamic power gradually. To decrease leakage power is becoming more and more important in low-power design. Base on the pact that PMOS transistors have an order of magnitude smaller gate leakage than NMOS ones, p-type complementary pass-transistor logic (P-CPL) and p-type differential cascade voltage switch logic (P-DCVSL) are proposed to reduce the static power in this paper. For an example, two full adders based on P-CPL and P-DCVSL circuits are verified. All circuits are simulated using 130 nm, 65 nm and 32 nm cmos processes. Their delay, power, and PDP are compared. Simulation results show that the P-CPL full adder consumes about 60%-80% of the dissipated energy of the static cmos and CPL ones at 200 MHz. The P-DCVSL full adder consumes 80%-90% of the dissipated energy of the DCVSL one at 200 MHz.

关键词： cmos technology Adders cmos logic circuits Switches Circuit simulation MOSFETs Gate leakage MOS devices Voltage cmos process

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4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for cmos logic Process Development, Monitor and Model

4K-cells Resistive and Charge-Base-Capacitive Measurement Te...

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IEEE International Conference on Microelectronic Test Structures

作者： Kelvin Y.Y. Doong Keh-Jeng Chang S.-C. Lin H.C. Tseng Akis Dagonis Samuel Pan Taiwan Semiconductor Manufacturing Company Limited Hsinchu Taiwan Department of Computer Science National Tsing Hua University Hsinchu Taiwan

To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for cmos logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32times16times8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1 fF for capacitive and 0.1 ohm for resistive systematic errors, and 7 times testing speed improvement.

关键词： logic testing logic arrays Current measurement cmos process cmos logic circuits Monitoring Semiconductor device modeling Semiconductor device measurement logic design Force measurement

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Low Dynamic Power High Performance Adder

Low Dynamic Power High Performance Adder

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International Conference on Future Computer and Communication, ICFCC

作者： M. Nadi Senejani M. Hosseinghadiry M. Miryahyaei Department of Computer Engineering Islamic Azad University Ashtian Branch Ashtian Iran Department of Computer Engineering Islamic Azad University Arak Branch Arak Iran

This paper presents the design of high performance low dynamic power circuits using a new cmos dynamic logic family, and analyzes power and performance of them, and compares the proposed logic to standard cmos dynamic logic. Results show that the dynamic power reduces at least 26% and the performance improves at least 4.6 times for a 32 bits ripple carry adder in comparison to standard domino logic. In other hand charge redistribution, limitation of non-inverting only logic and need for output inverter problems of domino logic are completely eliminated.

关键词： cmos logic circuits logic design logic devices Adders Pulse inverters Circuit analysis computing High performance computing Power engineering computing Design engineering Power engineering and energy

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Ultra low-power sequential circuit implementation by a Quasi-Static Single phase Adiabatic Dynamic logic (SPADL)

Ultra low-power sequential circuit implementation by a Quasi...

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IEEE Region 10 International Conference TENCON

作者： M. Chanda A. Dandapat H. Rahaman Advance VLSI Design Centre ECE Department MSIT Kolkata India ETCE Department Jadavpur University India IT Department Bengal Engineering and University India

This implementation of sequential logic circuits by using a novel quasi-static single-phase adiabatic dynamic logic (SPADL) has been presented. SPADL uses only a single sinusoidal source as supply-clock. This not only ensures lower energy dissipation, but also simplifies the clock design which would be otherwise more complicated due to the signal synchronization requirement. Simplicity and static logic resembled characteristics of SPADL logic, substantially decreases circuit complexity with improved driving ability and circuit robustness. A practical adiabatic asynchronous sequential circuit based on the energy efficient SPADL is implemented with TSMC 0.18 ¿m technology. Spice simulation shows that SPADL 8421 BCD code up counter circuits consume only 30% and 15% energy of single phase clocked adiabatic logic (an existing single-phase based energy recovery logic), and static cmos at 100 MHz. Both simulation and measurement results verify the functionality of such logic, making it suitable for implementing energy-aware and performance-efficient sequential circuit.

关键词： Sequential circuits cmos logic circuits Clocks logic circuits Circuit simulation Energy dissipation Signal design Synchronization Complexity theory Robustness

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Optimization of Power/Ground network considering area, performance and power consumption

Optimization of Power/Ground network considering area, perfo...

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Asia Pacific Conference on Postgraduate Research in Microelectronics & Electronics (PrimeAsia)

作者： Takahiro Watanabe Yuehui Shi Donghua Wu Zhiguo Bao Graduate school of IPS Shanghai University Waseda University China Fukuoka Japan Dept. of Math. Shanghai Univ. Waseda Univ. Shanghai China Waseda Daigaku Shinjuku-ku Tokyo JP

Due to the importance of power/ground network, lots of researches have been made on it. But they only focused on the minimal area of it. By discussion on the relation among Vdd, performance and power consumption, this paper proposes an optimal algorithm using GA and SLP method where area, performance and power consumption can be simultaneously evaluated. As a result, the power/ground network is designed by adjusting the wire width to supply the proper Vdds. The convergence of the algorithm is proved. Experimental results and simulations also show that the proposed algorithm can produce a good power/ground network.

关键词： Energy consumption Power supplies cmos logic circuits Mathematics Educational institutions Wire Convergence Design optimization Network topology Wiring

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A 1.2-mW cmos frequency synthesizer with fully-integrated LC VCO for 400-MHz medical implantable transceivers

A 1.2-mW CMOS frequency synthesizer with fully-integrated LC...

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IEEE Symposium on Radio Frequency Integrated circuits (RFIC)

作者： Alessandro Italia Giuseppe Palmisano Facoltà di Ingegneria DIEES Università di Catania Catania Italy

ISBN: (纸本)9781424433773

An ultra low-power frequency synthesizer for 400-MHz medical implantable transceivers was designed and fabricated in a 0.13-mum cmos technology. The circuit is implemented by means of an integer-N phase-locked loop, which features a fully-integrated LC VCO and 160/480-kHz programmable channel steps. The frequency synthesizer exhibits a phase noise better than -96 dBc/Hz at 100-kHz offset frequency for all the supported channels. The measured settling time is around 500 muS and the reference spurs are lower than -52 dBc. The power consumption of the frequency synthesizer is only 1.2 mW from a 1.2-V supply.

关键词： Frequency synthesizers Voltage-controlled oscillators Transceivers Phase locked loops cmos technology Energy consumption cmos logic circuits Phase noise Medical services Charge pumps

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