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检索条件"主题词=CMOS Logic Circuits"

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Implementation aspects of fault-tolerant logic built with single-electron devices

Implementation aspects of fault-tolerant logic built with si...

引用

Norchip

作者： Jacek Flak Mika Laiho VTT Technical Research Center of Finland Finland Microelectronics Laboratory University of Turku Turku Finland

This paper presents a single-electron tunneling (SET) device implementation of gates needed to build a nanoscale logic array for fault-tolerant computing. The proposed architecture is based on a regular array of locally interconnected SET gates controlled by cmos peripheries. Embedded hardware and information redundancies help to surmount the limited reliability of nanodevices. Such a logic system can be versatile due to binary programmable interconnections. Gate structures designed for SET technology are presented and their simulation results are discussed.

关键词： Fault tolerance logic devices Single electron devices cmos logic circuits logic arrays Tunneling Nanoscale devices Programmable logic arrays Computer architecture Hardware

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Multi-standard carrier generator with cmos logic divider

Multi-standard carrier generator with CMOS logic divider

引用

Midwest Symposium on circuits and Systems (MWSCAS)

作者： Seonghan Ryu Department of Information and Communication Engineering Hannam University Daejeon South Korea

A multi standard carrier generator chain satisfying all requirements of phase noise and frequency range for Quad-band GSM/EDGE and WCDMA standards is presented. It adopts a VCO utilizing bond-wire inductors with high-quality factor, an 8-bit coarse tune capbank for low VCO gain. cmos logic dividers are also adopted in this LO chain to meet the most stringent phase noise specification of GSM. The proposed divider structure also shows very wide tuning range of self oscillation frequency (0.54 to 2.44 GHz). The proposed LO chain is implemented in 0.13 mum cmos technology. The measured tuning range is about 22% (3.25 to 4.05 GHz). The LO chain exhibits a phase noise of -126, -136 and -164 dBc/Hz measured respectively at 400 KHz, 1 MHz and 20 MHz offset from 900 MHz Carrier.

关键词： cmos logic circuits Phase noise GSM Voltage-controlled oscillators Tuning cmos technology Frequency Multiaccess communication Bonding Inductors

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Nanoscale reconfigurable computing using non-volatile 2-D STTRAM array

Nanoscale reconfigurable computing using non-volatile 2-D ST...

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IEEE Conference on Nanotechnology

作者： Somnath Paul Subho Chatterjee Saibal Mukhopadhyay Swarup Bhunia Department of EECS Case Western Reserve University Cleveland USA Department of ECE Georgia Institute of Technology Atlanta USA

ISBN: (纸本)9781424448326

In this paper, we investigate the combination of a novel computing paradigm referred to as Memory Based Computing (MBC) and an emerging non-volatile nanoscale memory technology, namely Spin-Torque Transfer Random Access Memory (STTRAM), to build a reconfigurable nanocomputing framework with high integration density, robustness and energy-delay efficiency. MBC uses a 2-D memory array as underlying computing element. Noting the read-dominant access pattern in MBC, we optimize the STTRAM cells to increase the energy-delay efficiency. Further, exploiting the asymmetric nature of the cells, we introduce the notion of preferential storage which optimizes the cell performance for `1' over `0' and skew the LUT content toward `1' for improved energy-delay product (EDP).

关键词： Magnetic tunneling Nonvolatile memory Table lookup logic arrays cmos logic circuits Magnetization Magnetic switching logic circuits Integrated circuit interconnections Magnetic separation

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An integrated 20-bit 33/5M events/s AER sensor interface with 10ns time-stamping and hardware-accelerated event pre-processing

An integrated 20-bit 33/5M events/s AER sensor interface wit...

引用

IEEE Biomedical circuits and Systems (BIOCAS)

作者： Michael Hofstätter Peter Schön Christoph Posch AIT - Austrian Institute of Technology Vienna Austria AIT — Austrian Institute of Technology Vienna Austria

This paper presents a custom data bridge that interfaces the continuous-time world of asynchronous address-events (AER) to the realm of conventional digital data processing. The main focus in the design of the interface was on precisely maintaining the inherent timing information of AER sensor data while providing robust peak-rate handling, DMA functionality and a novel event-rate dependent system control mechanism. The sensor interface can be integrated with standard cmos logic in an AER processing system-on-chip and implements hardware-accelerated event pre-processing including pre-FIFO high-resolution time-stamping, address masking for ROI and event-rate dependent IRQ generation without loading a downstream processing device. The sensor interface has been implemented in a 0.18 ¿m cmos process and achieves peak AER event rates of 33M events/sec and sustained AER event rates of 5.125 M events/sec at 10 ns time-stamp resolution. We discuss design considerations and implementation details and show measurement results from the fabricated chip.

关键词： Sensor systems cmos process Bridges Data processing Timing Robust control Control systems cmos logic circuits logic devices System-on-a-chip

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A novel reconfigurable operator based IC design methodology for multimedia processing

A novel reconfigurable operator based IC design methodology ...

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IEEE Region 10 International Conference TENCON

作者： Dai Peng Wang Xin'an Zhang Xing Key Lab of Integrated Microsystem Science & Engineering Applications Shenzhen Graduate School of Peking University Shenzhen P. R. China

Currently the DSP applications such as multimedia processing raise the demands to IC designers for more flexibility, higher performance and shorter time-to-market. To solve these problems, this paper proposed a novel reconfigurable operator based IC design methodology for multimedia applications. Four kinds of reconfigurable operators and their logic meanings are introduced in this paper as well as the design flow. An archetypal reconfigurable circuit with 4*4 reconfigurable computing operator, reALU, is implemented in our research using SMIC 0.18 um cmos, achieving the performance 2.4 GOPS at 150 Mhz at 1.62 v. Several algorithms such as SAD and DCT are mapped into the array processor, which show the better performance than the traditional digital signal processors.

关键词： Design methodology Application specific integrated circuits Digital signal processing Time to market cmos logic circuits logic design Reconfigurable logic Signal processing algorithms Discrete cosine transforms Digital signal processors

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Soft error injection using advanced switch-level models for combinational logic in nanometer technologies

Soft error injection using advanced switch-level models for ...

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International Conference on Microelectronics, ICM

作者： Prabhleen K. Kalkat Reza Sedaghat Jalal Mohammad Chikhe Reza Javaheri Department of Electrical and Computer Engineering Ryerson University Toronto ONT Canada

Due to technology scaling, modern digital systems are becoming more prone to single-event transients (SETs) caused by radiation strikes in cmos logic devices. This has led to the need for better soft error detection methods in order to increase the reliability of logic circuits in nanometer technologies. Present day soft error detection techniques assume that soft errors occur due to voltage pulses which change the logic state of a transistor node. A novel soft error detection concept is used, assuming that voltage fluctuations smaller than logic threshold can eventually result in soft errors. Advanced switch-level models were designed which mimic important characteristics of transistor-level circuits like bidirectional signal flow, driving strength variations and node capacitances and use verilog driving strengths to model different voltage values. The resulting switch-level models eliminate the complexity associated with state-of-art transistor level simulators while achieving desired amount of accuracy and faster simulation. The aim of this paper is to interpret various parameters used in these strength-based switch models in order to find an efficient way of injecting transients into complex logic circuits. The approach has been evaluated experimentally by creating a simulation environment which allows transient injection at internal nodes of switch-level circuits and injecting a wide range of input test vectors to ISCAS'85 benchmarks. The simulation results show that transient injection at drains of switch-level circuits gives better results in terms of accuracy and prevents over-estimation of soft error rate calculations as compared to injection at gates of transistors.

关键词： Switching circuits Circuit simulation logic devices cmos technology cmos logic circuits logic circuits Voltage Transistors Switches Circuit testing

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Low voltage precharge cmos logic

Low voltage precharge CMOS logic

引用

IEEE Design and Diagnostics of Electronic circuits and Systems (DDECS)

作者： Yngvar Berg Omid Mirmotahari Microelectronic systems Department of Informatics University of Oslo Norway

In this paper we present ultra low voltage low power cmos logic. The low power gate may be configured or recharged to high speed or low power compared to a complementary inverter. The low power logic presented in this paper resembles precharge cmos logic. For a low supply voltage a sleep mode configuration is presented which may reduce the power consumption to less than 0.5% of a complementary inverter. A sleep mode configuration of the low power logic is presented and a keeper function is added to increase the noise margin and reduce the static power consumption. Simulated data for a STM 90 nm process using Spectre simulator provided by Cadence is included.

关键词： Low voltage cmos logic circuits Energy consumption Inverters Threshold voltage Leakage current Noise reduction Circuit simulation Dynamic voltage scaling Circuit synthesis

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A capacitive coupling interface with high sensitivity for wireless wafer testing

A capacitive coupling interface with high sensitivity for wi...

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IEEE International Conference on 3D System Integration, 3DIC

作者： Gil-Su Kim Makoto Takamiya Takayasu Sakurai Institute of Industrial Science University of Tokyo Tokyo Japan

A high-sensitivity capacitive-coupling interface is presented for wireless wafer testing systems. The transmitter is a buffer that drives the transmitter pad, and the receiver converts the data with various logic thresholds to that with optimum logic threshold. The receiver with the optimum logic threshold achieves the highest sensitivity of 25 mV at the data rate of 2 Gb/s in 0. 18 mum cmos. The proposed receiver increases the communication distance over 4 times while providing tolerance against the distance-voltage-area variations.

关键词： Wireless sensor networks Capacitance Couplings Transmitters Atherosclerosis System testing cmos logic circuits Bandwidth Voltage Inductors

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Functional mapping for nanodevice-based architectures

Functional mapping for nanodevice-based architectures

引用

International Conference on Microelectronics, ICM

作者： M. Amadou S. Le Beux G. Nicolescu I. O'Connor École Polytechnique de Montréal Canada École Centrale de Lyon Institut de Nanotechnologies de Lyon France

Recently, technology advancement led to the emergence of nanodevice-based architectures. By exploiting the fine-grain dynamic reconfigurability of these logic cells, nanodevice-based architectures are expected, compared to conventional architectures, to reduce area and cost, and improve performance over a broad range of applications. In order to explore the potential of these architectures, the definition of new CAD tools is required. This paper discusses the challenges for system-level exploration for nanodevice-based architectures and proposes an approach enabling automatic application partitioning and mapping for these architectures.

关键词： Reconfigurable logic Costs FETs Field programmable gate arrays cmos logic circuits Integrated circuit interconnections Partitioning algorithms Iterative algorithms cmos technology Prototypes

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Novel low-power 1-bit full adder design

Novel low-power 1-bit full adder design

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Chuen-Yau Chen Yung-Pei Chou Department of Electrical Engineering National University of Kaohsiung Kaohsiung Taiwan

This paper propose a 1-bit low-power full adder that is designed by taking the advantage of the concept of pass-transistor logic and the concept of dual-threshold domino logic. The concept of pass-transistor logic is used to design the circuit generating the sum signal such that the number of transistors can be reduced. The concept of dual-threshold domino logic is adapted to design the circuit generating the carryout signal such that the operation can be speeded up. This full adder was designed with a TSMC 0.18-mum 1P6M cmos process. The HSPICE simulation results show that this design achieves a superior performance with a power-delay product of 48.98 fJ for the SUM circuit and 16.19 fJ for the CARRYOUT circuit at 1.8-V supply voltage.

关键词： Adders logic design cmos logic circuits Energy consumption Clocks MOSFETs logic circuits cmos technology Signal design Signal generators

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