检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,880 篇 会议
644 篇 期刊文献
3 篇 学位论文

馆藏范围

4,527 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,168 篇 工学
- 821 篇 电气工程
- 351 篇 电子科学与技术（可...
- 247 篇 计算机科学与技术...
- 51 篇 材料科学与工程（可...
- 51 篇 控制科学与工程
- 50 篇 核科学与技术
- 36 篇 信息与通信工程
- 30 篇 软件工程
- 25 篇 机械工程
- 24 篇 仪器科学与技术
- 4 篇 生物医学工程（可授...
- 3 篇 光学工程
- 1 篇 力学（可授工学、理...
- 1 篇 动力工程及工程热...
- 1 篇 建筑学
- 1 篇 化学工程与技术
- 1 篇 石油与天然气工程
- 1 篇 交通运输工程
- 1 篇 网络空间安全
100 篇 理学
- 77 篇 物理学
- 18 篇 系统科学
- 6 篇 化学
- 1 篇 生物学
27 篇 管理学
- 27 篇 管理科学与工程(可...
5 篇 医学
- 4 篇 临床医学
- 1 篇 基础医学(可授医学...
- 1 篇 特种医学
3 篇 教育学
- 3 篇 教育学
1 篇 文学
- 1 篇 新闻传播学
1 篇 艺术学
- 1 篇 设计学（可授艺术学...

主题

4,527 篇 cmos logic circu...
1,837 篇 cmos technology
997 篇 logic circuits
899 篇 logic design
782 篇 clocks
773 篇 voltage
721 篇 logic devices
640 篇 logic gates
633 篇 cmos process
609 篇 energy consumpti...
518 篇 circuit simulati...
504 篇 delay
500 篇 very large scale...
499 篇 circuit testing
447 篇 switches
420 篇 semiconductor de...
410 篇 power dissipatio...
365 篇 threshold voltag...
361 篇 logic testing
339 篇 mosfets

机构

48 篇 ibm thomas j. wa...
25 篇 faculty of infor...
22 篇 texas instrument...
21 篇 department of el...
17 篇 central research...
17 篇 department of el...
16 篇 philips research...
16 篇 department of el...
15 篇 department of in...
14 篇 school of electr...
14 篇 intel corporatio...
14 篇 infineon technol...
13 篇 department of el...
13 篇 massachusetts in...
12 篇 lsi logic corpor...
12 篇 department of el...
12 篇 department of el...
10 篇 intel corporatio...
10 篇 semiconductor de...
10 篇 imec leuven

作者

37 篇 k. roy
25 篇 jianping hu
18 篇 m. hashizume
18 篇 m.i. elmasry
17 篇 y. berg
16 篇 j.b. kuo
16 篇 t. tamesada
15 篇 c. sechen
13 篇 d. al-khalili
13 篇 k.w. current
13 篇 s. vassiliadis
12 篇 kuo-hsing cheng
12 篇 sung-mo kang
12 篇 m. shams
12 篇 yusuf leblebici
11 篇 a. afzali-kusha
11 篇 f. matsuoka
11 篇 n.k. jha
11 篇 e.j. mccluskey
11 篇 j. figueras

语言

4,435 篇 英文
51 篇 其他
41 篇 中文

检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是551-560 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Fault tolerant reversible logic synthesis: Carry look-ahead and carry-skip adders

Fault tolerant reversible logic synthesis: Carry look-ahead ...

引用

International Conference on Advances in Computational Tools for Engineering Applications, ACTEA

作者： Md. Saiful Islam Muhammad Mahbubur Rahman Zerina Begum Mohd. Zulfiquar Hafiz Institute of Information Technology University of Dhaka Dhaka Bangladesh Department of Computer Science American International University-Bangladesh Dhaka Bangladesh

Irreversible logic circuits dissipate heat for every bit of information that is lost. Information is lost when the input vector cannot be recovered from its corresponding output vector. Reversible logic circuit naturally takes care of heating because it implements only the functions that have one-to-one mapping between its input and output vectors. Therefore reversible logic design becomes one of the promising research directions in low power dissipating circuit design in the past few years and has found its application in low power cmos design, digital signal processing and nanotechnology. This paper presents the efficient approaches for designing reversible fast adders that implement carry look-ahead and carry-skip logic. The proposed 16-bit high speed reversible adder will include IG gates for the realization of its basic building block. The IG gate is universal in the sense that it can be used to synthesize any arbitrary Boolean-functions. The IG gate is parity preserving, that is, the parity of the inputs matches the parity of the outputs. It allows any fault that affects no more than a single signal readily detectable at the circuit's primary outputs. Therefore, the proposed high speed adders will have the inherent opportunity of detecting errors in its output side. It has also been demonstrated that the proposed design offers less hardware complexity and is efficient in terms of gate count, garbage outputs and constant inputs than the existing counterparts.

关键词： Fault tolerance Adders Circuit synthesis logic circuits logic design cmos logic circuits Heating cmos digital integrated circuits cmos process Process design

来源：评论

学校读者我要写书评

暂无评论

Fast lock scheme for phase-locked loops

Fast lock scheme for phase-locked loops

引用

Custom Integrated circuits Conference (CICC)

作者： Amir Bashir Jing Li Kiran Ivatury Naveed Khan Nirav Gala Noam Familia Zulfiqar Mohammed Intel Corporation Folsom CA USA Intel Corporation Jerusalem Israel

This paper describes a fast lock scheme for phaselocked loops (PLLs). The proposed scheme utilizes mostly digital logic and control to achieve significant reduction in PLL lock acquisition time, which enables dynamic power cycling for various sub-systems on SOC designs. Multiple Self-Bias PLLs having fast lock schemes were designed to operate at VCO frequencies from 1.6 GHz to 5 GHz, and fabricated using 65 nm cmos process. Silicon measurements indicate up to 75% reduction in worst-case PLL lock times over the device operating conditions.

关键词： Phase locked loops cmos logic circuits logic design Digital control Voltage-controlled oscillators Frequency cmos process Silicon

来源：评论

学校读者我要写书评

暂无评论

Influence of gate oxide short defects on the stability of minimal sized SRAM core-cell by applying non-split models

Influence of gate oxide short defects on the stability of mi...

引用

International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： J.M. Galliere F. Azais M. Renovell L. Dilillo Polytech' Montpellier University of Montpellier 2 Montpellier France LIRMM CNRS University of Montpellier 2 Montpellier France

In this paper, we study the impact of gate oxide short (GOS) defects in SRAM core-cells in terms of stability in static condition. Existing studies have applied split GOS models that require the use of non-realistic oversized designs. The novelty of this research is the application of a non-split GOS model, which allows the study of the electric deviation of the behavior of realistic minimal sized SRAM core-cells. The results of extensive simulations are produced, by taking in account defect variations in terms of position in the transistor gate oxide and resistance.

关键词： Stability Random access memory cmos logic circuits Substrates Joining processes Electric resistance Semiconductor device reliability Semiconductor devices Isolation technology Degradation

来源：评论

学校读者我要写书评

暂无评论

Analysis and evaluation of layout density of FinFET logic gates

Analysis and evaluation of layout density of FinFET logic ga...

引用

International Conference on Microelectronics, ICM

作者： Massimo Alioto Department of Information Engineering University of Sienna Siena Italy

In this paper, the layout density of FinFET logic gates is analyzed and compared to that of bulk cmos logic. Analysis starts from basic structures, including single- and multi-finger transistors, as well as stacked transistors. As opposite to previous work, four-terminal (4T) FinFETs are also explicitly taken into account. The analysis is extended to the physical design of a standard cell library in 65-nm technology. Comparison with bulk technology confirms that 3T FinFETs suffer from significant layout density degradation, as was previously observed in. Moreover, it is shown that 4T FinFETs have a considerably worse layout density, compared to 3T FinFETs and bulk transistors. The sources of the 3T-4T layout density degradation are also discussed. Finally, the mixed 3T-4T approach, which was recently proposed to reduce the leakage power, is investigated as a compromise between 3T and 4T FinFET circuits in terms of area.

关键词： FinFETs logic gates cmos logic circuits cmos technology Degradation Manufacturing processes Information analysis Libraries cmos process Silicon

来源：评论

学校读者我要写书评

暂无评论

Fundamental logics based on two phase clocked adiabatic static cmos logic

Fundamental logics based on two phase clocked adiabatic stat...

引用

IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Nazrul Anuar Yasuhiro Takahashi Toshikazu Sekine Graduate School of Engineering Gifu University Gifu Japan Department of Electrical and Electronic Engineering Gifu University Gifu Japan

ISBN: (纸本)9781424450909;9781424450916

This paper demonstrates some fundamental logic gates employing two phase clocked adiabatic static cmos logic (2PASCL) circuit techniques. We design and simulate NOT, NAND, NOR, and XOR logic gates on the basis of the 2PASCL topology using SPICE implemented using 0.18 ¿m CTX cmos technology. For NOT circuit, analytical and simulation values are compared. From the simulation results, we find that 2PASCL inverter logic can save up to 97% of dissipated energy as compared to that with a static cmos logic at transition frequencies of 10 to 100 MHz. Further, the power dissipation is the lowest when compared with other proposed simple adiabatic logic inverters. 2PASCL also achieves the highest fan-out performance. The results indicate that 2PASCL technology can be advantageously applied to low power digital devices operated at low frequencies, such as radio-frequency identifications (RFIDs), smart cards, and sensors.

关键词： cmos logic circuits Clocks Pulse inverters Circuit simulation cmos technology logic gates Frequency Radiofrequency identification logic design Circuit topology

来源：评论

学校读者我要写书评

暂无评论

Low-power 7.2 GHz complementary all-N-transistor logic using 90 nm cmos technology

Low-power 7.2 GHz complementary all-N-transistor logic using...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Chia-Hao Hsu Gang-Neng Sung Tuo-Yu Yao Chun-Ying Juan Yain-Reu Lin Chua-Chin Wang Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung Taiwan

ISBN: (纸本)9781424438273

This paper proposed an complementary all-N-transistor (CANT) comprising ANT logic and inverted ANT logic. In ANT logic's N-Block, the threshold voltage of the transistors is variable depending on the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-Block is increased to V DD -V thn to enhance the operation speed. In the pre-charge phase, the bulk voltage of the transistors in the N-Block is dropped to almost 0 V such that the subthreshold leakage current is reduced. By utilizing such a variable bulk voltage scheme in the proposed complementary ANT (CANT) logic, a 32-bit CLA is designed using TSMC 90 nm cmos process to verify the low power and high speed performance. The area of the proposed design is 0.0483 mm 2 and the power dissipation is 102 mW given a 7.2 GHz clock at the worst PVT condition.

关键词： cmos technology cmos logic circuits Pulse inverters Clocks Adders logic design Power dissipation Threshold voltage cmos process logic circuits

来源：评论

学校读者我要写书评

暂无评论

Sign-bit based architecture for OFDM Acquisition for multiple-standards

Sign-bit based architecture for OFDM Acquisition for multipl...

引用

Norchip

作者： Isael Diaz Leif Wilhelmsson Joachim Rodrigues Thomas Olsson Viktor Öwall Department of Electrical and Information Technology Lund University Lund Sweden Ericsson Research Limited Finland

This paper presents a hardware mapping of an auto-correlator for Orthogonal Frequency Division Multiplexing stage for three radio standards: LTE, DVB-H, and IEEE 802.11n. Hardware cost is minimized by using only the sign bit in the autocorrelation function. The frequency offset estimation procedure is dramatically simplified by reducing the phase of the envelope to ¿/2 resolution, which in turn reduces the need of specialized components. The architecture is synthesized towards a 65 nm low-leakage high threshold standard cell cmos library. The 1-bit architecture reports an area reduction of 90% for memories, 56% for the logic and a power dissipation reduction of 35%, when compared to an identical 8-bit implementation. The approximate area occupied by the architecture is 0.03 mm 2 . Power simulations for IEEE 802.11n packet reports a power dissipation of 42 ¿W.

关键词： OFDM Hardware Frequency estimation Power dissipation Digital video broadcasting Cost function Autocorrelation Phase estimation Libraries cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

A modern look at the cmos stuck-open fault

A modern look at the CMOS stuck-open fault

引用

Latin American Test Workshop, LATW

作者： Roberto Gomez Victor Champac Chuck Hawkins Jaume Segura Department Electronic Engineering National Institute for Astrophysics Optics and Electronics Puebla Mexico ECE Department University of New Mexico Albuquerque NM USA University of Balearic Islands Mallorca Spain

The stuck-open fault (SOF) is a difficult, hard failure mechanism unique to cmos technology [1-3]. Its detection requires a specific 2-vector pair that examines each transistor in the logic gate for an open defect in its drain and/or source. This defect defies a guaranteed 100% detection. We will show that this mostly discarded failure mechanism is very relevant to modern ICs. Current leakage in nanoscale technologies influence significantly the behavior of this fault.

关键词： Circuit faults cmos technology logic gates Failure analysis cmos logic circuits Capacitance Integrated circuit noise Leak detection Circuit testing Combinational circuits

来源：评论

学校读者我要写书评

暂无评论

All-optical reversible multiplexer

All-optical reversible multiplexer

引用

International Conference on Computers and Devices for Communication (CODEC)

作者： Goutam Kumar Maity Tanay Chattopadhyay Jitendra Nath Roy Santi Prasad Maity Calcutta Institute of Technology Uluberia Howrah W.B. India Mechanical operation stage II Kolaghat Thermal Power Station Midnapur (east) West Bengal India Department of Physics College of Engineering and Management Kolaghat Midnapur(east) West Bengal India Department of Information Technology Bengal Engineering and Science University Shibpur Howrah

The advantages of reversible logic systems and circuits have drawn a significant interest in recent years as a promising computing paradigm having application in low power cmos, quantum computing, nanotechnology, and optical computing. This paper proposes a novel reversible multiplexer circuit with the help of all-optical Toffoli and Feynman gate. Operational principle of reversible multiplexer is described and is supported with logical simulation.

关键词： Multiplexing Optical computing Josephson junctions logic circuits logic gates cmos logic circuits Quantum computing Thermal management Energy dissipation Optical buffering

来源：评论

学校读者我要写书评

暂无评论

Probabilistic metric of gate logical fault occurrence due to manufacturing inaccuracy of threshold logic gates for efficient testing

Probabilistic metric of gate logical fault occurrence due to...

引用

International Conference on Design and Technology of Integrated Systems in Nanoscale Era (DTIS)

作者： Tsuyoshi Shinogi Kanako Arakawa Terumine Hayashi Department of Electrical and Electronic Engineering Mie University Tsu Mie Japan

This paper proposes a precise metric of the occurrence of gate logical faults due to manufacturing inaccuracy of the weight and threshold values in threshold logic gates for effective and efficient testing. Based on probability density functions of the values of the manufactured weights and threshold, the probability of gate logical fault occurrence is calculated and used as the metric. The metric indicates the importance of the corresponding gate input pattern in testing of the threshold logic gate, and will be utilized for effective and efficient testing. We compare our proposed metric with a simple metric.

关键词： logic testing logic gates Probabilistic logic Circuit faults cmos logic circuits logic design logic circuits Automatic test pattern generation Pulp manufacturing Circuit testing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共453页 << < 52 53 54 55 56 57 58 59 60 61 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：