检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

3,880 篇 会议
644 篇 期刊文献
3 篇 学位论文

馆藏范围

4,527 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

1,168 篇 工学
- 821 篇 电气工程
- 351 篇 电子科学与技术（可...
- 247 篇 计算机科学与技术...
- 51 篇 材料科学与工程（可...
- 51 篇 控制科学与工程
- 50 篇 核科学与技术
- 36 篇 信息与通信工程
- 30 篇 软件工程
- 25 篇 机械工程
- 24 篇 仪器科学与技术
- 4 篇 生物医学工程（可授...
- 3 篇 光学工程
- 1 篇 力学（可授工学、理...
- 1 篇 动力工程及工程热...
- 1 篇 建筑学
- 1 篇 化学工程与技术
- 1 篇 石油与天然气工程
- 1 篇 交通运输工程
- 1 篇 网络空间安全
100 篇 理学
- 77 篇 物理学
- 18 篇 系统科学
- 6 篇 化学
- 1 篇 生物学
27 篇 管理学
- 27 篇 管理科学与工程(可...
5 篇 医学
- 4 篇 临床医学
- 1 篇 基础医学(可授医学...
- 1 篇 特种医学
3 篇 教育学
- 3 篇 教育学
1 篇 文学
- 1 篇 新闻传播学
1 篇 艺术学
- 1 篇 设计学（可授艺术学...

主题

4,527 篇 cmos logic circu...
1,837 篇 cmos technology
997 篇 logic circuits
899 篇 logic design
782 篇 clocks
773 篇 voltage
721 篇 logic devices
640 篇 logic gates
633 篇 cmos process
609 篇 energy consumpti...
518 篇 circuit simulati...
504 篇 delay
500 篇 very large scale...
499 篇 circuit testing
447 篇 switches
420 篇 semiconductor de...
410 篇 power dissipatio...
365 篇 threshold voltag...
361 篇 logic testing
339 篇 mosfets

机构

48 篇 ibm thomas j. wa...
25 篇 faculty of infor...
22 篇 texas instrument...
21 篇 department of el...
17 篇 central research...
17 篇 department of el...
16 篇 philips research...
16 篇 department of el...
15 篇 department of in...
14 篇 school of electr...
14 篇 intel corporatio...
14 篇 infineon technol...
13 篇 department of el...
13 篇 massachusetts in...
12 篇 lsi logic corpor...
12 篇 department of el...
12 篇 department of el...
10 篇 intel corporatio...
10 篇 semiconductor de...
10 篇 imec leuven

作者

37 篇 k. roy
25 篇 jianping hu
18 篇 m. hashizume
18 篇 m.i. elmasry
17 篇 y. berg
16 篇 j.b. kuo
16 篇 t. tamesada
15 篇 c. sechen
13 篇 d. al-khalili
13 篇 k.w. current
13 篇 s. vassiliadis
12 篇 kuo-hsing cheng
12 篇 sung-mo kang
12 篇 m. shams
12 篇 yusuf leblebici
11 篇 a. afzali-kusha
11 篇 f. matsuoka
11 篇 n.k. jha
11 篇 e.j. mccluskey
11 篇 j. figueras

语言

4,435 篇 英文
51 篇 其他
41 篇 中文

检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是581-590 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

A pure logic cmos based low power non-volatile random access memory for RFID application

A pure logic CMOS based low power non-volatile random access...

引用

International Conference on ASIC

作者： Yaru Yan Dong Wu Huijuan Liu Liyang Pan Jun Xu Institute of Microelectronics Tsinghua University Beijing China Institute of Microelectronics Tsinghua National Laboratory for Information Science and Technology Tsinghua University Beijing China

A 1.8V, 0.18 ¿m pure logic cmos based low power non-volatile random access memory for RFID application is developed in this paper. Low power consumption is achieved based on a novel two-dimension architecture and a series of power optimization methods. Simulation result shows that the power consumption for read and write operations is less than 160 ¿W and 560 ¿W respectively. The merits make it suitable for low power RFID .

关键词： cmos logic circuits Nonvolatile memory Random access memory Radiofrequency identification Switches Energy consumption Decoding Charge pumps Switching circuits Voltage

来源：评论

学校读者我要写书评

暂无评论

FPGA Implementation of a Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier

FPGA Implementation of a Decimal Floating-Point Accurate Sca...

引用

International Conference on Reconfigurable Computing and FPGAs (ReConFig)

作者： Malte Baesler Thomas Teufel Institute for Reliable Computing Hamburg University of Technology Hamburg Germany

Decimal floating point (DFP) operations are very important for applications, that cannot tolerate errors from conversions between binary and decimal formats, for instance scientific, commercial, financial and internet-based applications. In this paper we present a parallel decimal fixed-point multiplier, designed to exploit the features of FPGAs. Our multiplier is based on BCD recoding schemes, fast partial product generation and a BCD-4221 carry save adder reduction tree. Furthermore, we extend the multiplier with an accurate scalar product unit in order to provide an important operation with smallest possible rounding error as proposed in. Finally the design is implemented and tested on a Xilinx Virtex-II Pro FPGA platform.

关键词： Field programmable gate arrays Floating-point arithmetic Application specific processors Concurrent computing Testing Internet Roundoff errors Hardware Prototypes cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

Multiobjective optimization for transistor sizing of cmos logic standard cells using set-oriented numerical techniques

Multiobjective optimization for transistor sizing of CMOS lo...

引用

Norchip

作者： Matthias Blesken Ulrich Rückert Dominik Steenken Katrin Witting Michael Dellnitz System and Circuit Technology University of Paderborn Germany Applied Mathematics University of Paderborn Germany

The design of resource efficient integrated circuits (IC) requires solving a minimization problem of more than one objective given as measures of available resources. This multiobjective optimization problem (MOP) can be solved on the smallest unit, the standard cells, to improve the performance of the entire IC. The traditional way of sizing the transistors of a standard logic cell does not focus on the resources directly. In this work transistor sizing is approached via an MOP and solved by set-oriented numerical techniques. A comparison of the Pareto optimal designs to elements of a commercial standard cell library indicates that for some gates the performance can even be significantly improved.

关键词： cmos logic circuits logic gates logic design cmos technology cmos integrated circuits Inverters Design optimization Measurement standards Integrated circuit technology Mathematics

来源：评论

学校读者我要写书评

暂无评论

High performance 16-bit MCML multiplier

High performance 16-bit MCML multiplier

引用

European Conference on Circuit Theory and Design, ECCTD

作者： Yavuz Delican Avni Morgul Electrical Engineering Department Bogazici University Istanbul Turkey Electrical & Communications Engineering Department Bilkent University Istanbul Turkey

This paper presents a high performance 16times16 bit 2's complement multiplier using MOS current mode logic (MCML). A small library of MCML logic gates consisting of NAND/AND, XOR/XNOR, MUX and full adder are designed and optimized for low power and high-speed operation. Using these gates, a 16 bit MCML signed multiplier is designed and tested for 4 different supply current, in a UMC 0.18 mum cmos technology and VDD of 1.8V. According to our simulations, the highest current circuit works at 800 MHz and consumes 55 mW, while the lowest power operates at 250 MHz and consumes 16 mW. The circuits are either consume less power or operate up to a higher frequency compared to equivalent circuits in the literature. One of the most important advantages of this circuit is the absence of the power supply current spikes which makes the circuit very suitable for mixed mode designs. The multiplier consists of 7,268 transistors while a comparable cmos multiplier in the literature consists of 13,444 transistors.

关键词： Current supplies cmos technology Libraries logic gates cmos logic circuits logic design Adders Design optimization Circuit testing Circuit simulation

来源：评论

学校读者我要写书评

暂无评论

Analysis and design of ultra-low power subthreshold MCML gates

Analysis and design of ultra-low power subthreshold MCML gat...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Massimo Alioto Yusuf Leblebici Department of Information Engineering University of Sienna Siena Italy Microelectronic Systems Laboratory Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland

ISBN: (纸本)9781424438273

In this paper, ultra-low power current-mode subthreshold MOS current-mode logic (MCML) gates are discussed from a modeling and design perspective. A detailed analysis of the DC characteristics is presented, and the effect of process variations is analyzed in depth. Analysis allows for understanding the main limits of sub-threshold MCML gates in terms of delay/power variability. In particular, it is shown that process variations strongly affect the DC characteristics, and moderately impact delay and power consumption. Interestingly, delay and power variations are shown to be significantly reduced compared to typical values encountered in standard subthreshold cmos logic. Criteria to size transistors to keep variations within assigned bounds are also derived. Results of Monte Carlo simulations with a 65-nm cmos technology are reported to validate theoretical results.

关键词： cmos logic circuits Delay cmos technology Energy consumption Threshold voltage logic circuits Semiconductor device modeling MOSFETs Information analysis Design engineering

来源：评论

学校读者我要写书评

暂无评论

Design and reliability of a micro-relay technology for zero-standby-power digital logic applications

Design and reliability of a micro-relay technology for zero-...

引用

International Electron Devices Meeting (IEDM)

作者： Hei Kam Vincent Pott Rhesa Nathanael Jaeseok Jeon Elad Alon Tsu-Jae King Liu Department of EECS University of California Berkeley CA USA

ISBN: (纸本)9781424456390;9781424456406

Micro-electro-mechanical (MEM) relays recently have been proposed for ultra-low-power digital logic applications because their ideal switching behavior can potentially allow the supply voltage (V DD ) to be scaled down further than for cmos devices. This paper describes design techniques to achieve reliable (high-endurance) MEM relay operation. Prototype relays fabricated using a cmos-compatible process are demonstrated to operate with low surface adhesion force, adequately low on-state resistance (< 100 k¿) over a wide temperature range (20°C-200°C), and >10 9 on/off switching cycles in N 2 ambient without stiction- or welding-induced failure. Measured characteristics are well predicted by both ANSYS simulations and an analytical model. Using the calibrated analytical model, scaled relay technology is projected to achieve >10× energy savings over comparably sized cmos technology at throughputs up to ~100 MHz.

关键词： Microrelays logic design cmos technology Digital relays Analytical models cmos logic circuits logic devices Surface resistance Voltage Prototypes

来源：评论

学校读者我要写书评

暂无评论

Towards a balanced ternary FPGA

Towards a balanced ternary FPGA

引用

IEEE International Conference on Field-Programmable Technology (FPT)

作者： Paul Beckett Electrical & Computer Engineering RMIT University Melbourne Australia

We propose and analyze an organization for a field-programmable gate array structure that operates using a balanced ternary logic system where the logic set {±1, 0} maps directly to equivalent voltage levels {±1.0V, 0.0V}. circuits for basic components such as a ternary buffer, flip-flop and LUT are described based on the characteristics of a commercial silicon-on-sapphire process that offers multiple simultaneous transistor thresholds. A simple example of a balanced ternary FIR filter is mapped to the FPGA and some preliminary estimates made of its performance and area.

关键词： Field programmable gate arrays Multivalued logic logic arrays Table lookup Finite impulse response filter Voltage Flip-flops Arithmetic Adaptive filters cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

Evaluation of energy-recovering interconnects for low-power 3D stacked ICs

Evaluation of energy-recovering interconnects for low-power ...

引用

IEEE International Conference on 3D System Integration, 3DIC

作者： P. Asimakopoulos G. Van der Plas A. Yakovlev P. Marchal School of EECE Newcastle University UK IMEC Belgium

Energy-recovering schemes have been proposed in the literature as an alternative approach to low-power design, while their performance has been demonstrated to be extremely promising when driving large capacitive loads, such as clock distribution networks. This work investigates the potential of the energy-recovering methodology for improving the energy efficiency of through-silicon via (TSV) interconnects in 3D ICs.

关键词： Through-silicon vias Integrated circuit interconnections Energy dissipation Energy efficiency cmos logic circuits Frequency Parasitic capacitance Clocks Driver circuits Drives

来源：评论

学校读者我要写书评

暂无评论

Integration of tall triple-gate devices with inserted-Ta/sub x/N/sub y/ gate in a 0.274/spl mu/m/sup 2/ 6T-SRAM cell and advanced cmos logic circuits

Integration of tall triple-gate devices with inserted-Ta/sub...

引用

Symposium on VLSI Technology

作者： L. Witters N. Collaert A. Nackaerts M. Demand S. Demuynek C. Delvaux A. Lauwers C. Baerts S. Beckx W. Bouilart S. Brus B. Degroote J.F. de Marneffe A. Dixit K. De Meyer M. Ercken M. Goodwin E. Hendrickx N. Heylen P. Jaenen D. Laidler P. Leray S. Locorotondo M. Maenhoudt M. Moclants I. Pollentier K. Ronse R. Rooyackers J. Van Aelst G. Vandenberghe T. Vandeweyer S. Vanhaelemeersch M. Van Hove J. Van Olmen S. Verhaegen J. Versluijs C. Vrancken V. Wiaux P. Willems J. Wouters M. Jurezak S. Biesemans IMEC Leuven Belgium Interuniversitair Micro-Elektronica Centrum Leuven Vlaams-Brabant BE K.U.Leuven ESAT-INSYS Heverlee Belgium Texas Instruments Inc. Dallas TX USA Philips Research Leuven Leuven Belgium

We present the fabrication process of a fully functional 0.274/spl mu/m2 6T-SRAM cell with inserted-Ta/sub x/N/sub y/ tall tripple gate devices. Several advancements over our previous report by A. Naekaerts et al. (2004) are: reduction of the 6T-SRAM cell size from 0.314 to 0.274/spl mu/m2 using further litho process optimizations; insertion of 5nm TaN-based layer in the gate stack of the cell devices; improved OPC for CD control and integration of SRAM and logic. A high static noise margin of 216mV at 1.0V has been achieved with devices having a Lg=37nm. This is the smallest 6T-SRAM cell with MG devices reported so far.

关键词： cmos logic circuits Random access memory Layout Lighting Fabrication logic circuits Instruments Size control logic devices Noise reduction

来源：评论

学校读者我要写书评

暂无评论

Electric field for detecting open leads in cmos logic circuits by supply current testing

Electric field for detecting open leads in CMOS logic circui...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： M. Hashizume M. Ichimiya H. Yotsuyanagi T. Tamesada Faculty of Engineering University of Tokushima Tokushima Japan

Open leads are one type of defect occurring frequently when logic circuits are implemented on printed circuit boards (PCBs) with ICs. A powerful supply current test method has been proposed for detecting an open lead in a cmos logic circuit. The method is based on the supply current of a circuit under test which flows when a time-varying electric field is supplied from the outside of the circuit. The paper proposes a time-varying electric field which enables us to detect open leads in a cmos logic circuit with an inexpensive test setup.

关键词： Circuit testing cmos logic circuits Current supplies logic testing Lead Circuit faults Voltage logic circuits Pins Image processing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共453页 << < 55 56 57 58 59 60 61 62 63 64 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：