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High performance low power cmos dynamic logic for arithmetic circuits

MICROELECTRONICS JOURNAL 2007年第4-5期38卷 482-488页

作者： Navarro-Botello, Victor Montiel-Nelson, Juan A. Nooshabadi, Saeid GIST Dept Informat & Commun Kwangju South Korea Univ Las Palmas Gran Canaria Inst Appl Microelect E-35017 Las Palmas Gran Canaria Spain

This paper presents the design of high performance and low power arithmetic circuits using a new cmos dynamic logic family, and analyzes its sensitivity against technology parameters for practical applications. The proposed dynamic logic family allows for a partial evaluation in a computational block before its input signals are valid, and quickly performs a final evaluation as soon as the inputs arrive. The proposed dynamic logic family is well suited to arithmetic circuits where the critical path is made of a large cascade of inverting gates. Furthermore, circuits based on the proposed concept perform better in high fanout and high switching frequencies due to both lower delay and dynamic power consumption. Experimental results, for practical circuits, demonstrate that low power feature of the propose dynamic logic provides for smaller propagation time delay (3.5 times), lower energy consumption (55%), and similar combined delay, power consumption and active area product (only 8% higher), while exhibiting lower sensitivity to power supply, temperature, capacitive load and process variations than the dynamic domino cmos technologies. (c) 2007 Elsevier Ltd. All rights reserved.

关键词： dynamic logic cmos digital integrated circuits cmos logic circuits low power arithmetic circuits high speed arithmetic circuits

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IMPROVED DYNAMIC CURRENT MODE logic FOR LOW POWER APPLICATIONS

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JOURNAL OF circuits SYSTEMS AND COMPUTERS 2008年第2期17卷 183-190页

作者： Ramakrishnan, S. Lau, K. T. Nanyang Technol Univ Ctr Integrated Circuits & Syst Sch Elect & Elect Engn Singapore S639798 Singapore

In this paper, a newly improved dynamic current mode logic (I-DyCML) is proposed to achieve low power dissipation. The principle used in I-DyCML is the reduction of the leakage current by turning the part of the circuit to "standby mode", when not in use, while achieving lower dynamic power during the active mode. HSpice simulations show that I-DyCML saves up to 15-30% of the total power dissipation when compared to Dynamic Current mode logic.

关键词： Current mode logic low power cmos dynamic CML cmos logic circuits

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High-performance noise-tolerant circuit techniques for cmos dynamic logic

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IET circuits DEVICES & SYSTEMS 2008年第6期2卷 537-548页

作者： Frustaci, F. Corsonello, P. Perri, S. Cocorullo, G. Univ Calabria Dept Elect Comp Sci & Syst I-87036 Arcavacata Di Rende CS Italy

Dynamic cmos gates are widely exploited in high-performance designs because of their speed. However, they suffer from high noise sensitivity. The main reason for this is the sub-threshold leakage current flowing through the evaluation network. This problem becomes more and more severe with continuous scaling of the technology. A new circuit technique for increasing the noise tolerance of dynamic cmos gates is studied. A comparison with previously reported schemes is presented. Simulations proved that, when 90 nm cmos technology is used to realise wide fan-in gates, the proposed design technique can achieve the highest level of noise robustness. A 16 bits OR gate designed as proposed here shows a maximum unity noise gain of 675 mV, a computational delay of similar to 115 ps and an energy dissipation of similar to 33 fJ. Moreover, at the parity of energy-delay product (EDP), the novel approach achieves a noise robustness 10% higher than the most efficient technique existing in the literature, whereas, at the parity of noise robustness, it exhibits an EDP 33% lower.

关键词： OR gate voltage 675 mV dynamic cmos gates size 90 nm logic gates cmos technology energy-delay product sub-threshold leakage current cmos dynamic logic cmos logic circuits high-performance noise-tolerant circuit techniques

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Delay modeling of cmos/CPL logic circuits

Delay modeling of CMOS/CPL logic circuits

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Yuanzhong Wan M. Shams Department of Electronics Carleton University Ottawa ONT Canada

Effective optimization methods aimed at achieving maximal speeds in single-technology logic circuits are widely available but systematic ways suitable for circuits involving mixtures of logic families are not. The combination of standard cmos with CPL (complementary pass-transistor logic) is examined with an eye to finding the best structure and the best insertion points for cmos buffers intended to improve a CPL chain's propagation time and drive capability.

关键词： Semiconductor device modeling cmos logic circuits logic circuits MOS devices Capacitance MOSFETs Delay effects Voltage Latches Degradation

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Signed-digit cmos (SD-cmos) logic circuits with dynamic operation

Signed-digit CMOS (SD-CMOS) logic circuits with dynamic oper...

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International Symposium on Multiple-Valued logic

作者： H. Fukuda New Japan Radio Company Limited Japan

This paper proposes a design for signed-digit cmos (SD-cmos) basic circuits, such as a driver circuit, an inverter circuit, and a full-adder circuit, and describes a parallel multiplier circuit capable of high-speed operation with a time of about 10 nsec independent of the bit length. The proposed cmos basic circuits utilize a multi-voltage power supply to enable dynamic operation with pre-charged output terminals at signal level 0 (VDD1). This design methodology is applicable to arithmetic circuits for highly accurate, high-speed processors.

关键词： cmos logic circuits logic circuits Driver circuits Inverters Power supplies Arithmetic cmos digital integrated circuits Adders Voltage control Design methodology

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Integrated circuits & Manufacturing - Advanced cmos logic and SoC Platforms

Integrated Circuits & Manufacturing - Advanced CMOS Logic an...

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International Electron Devices Meeting (IEDM)

作者： Jon Cheek John Pellerin Freescale Semiconductor Advanced Micro Devices

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Fault-tolerant logic gates using neuromorphic cmos circuits

Fault-tolerant logic gates using neuromorphic CMOS Circuits

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Ph.D. Research in Microelectronics and Electronics (PRIME)

作者： Neil Joye Alexandre Schmid Yusuf Leblebici Tetsuya Asai Yoshihito Amemiya Microelectronic Systems Laboratory Swiss Federal Institute of Technology Lausanne Switzerland Graduate School of Information Science and Technology Hokkaido University Sapporo Japan

Fault-tolerant design methods for VLSI circuits, which have traditionally been addressed at system level, will not be adequate for future very-deep submicron cmos devices where serious degradation of reliability is expected. Therefore, a new design approach has been considered at low level of abstraction in order to implement robustness and fault-tolerance into these devices. Moreover, fault tolerant properties of multi-layer feed-forward artificial neural networks have been demonstrated. Thus, we have implemented this concept at circuit-level, using spiking neurons. Using this approach, the NOT, NAND and NOR Boolean gates have been developed in the AMS 0.35 mum cmos technology. A very straightforward mapping between the value of a neural weight and one physical parameter of the circuit has also been achieved. Furthermore, the logic gates have been simulated using SPICE corners analysis which emulates manufacturing variations which may cause circuit faults. Using this approach, it can be shown that fault-absorbing neural networks that operate as the desired function can be built.

关键词： cmos logic circuits Fault tolerance logic gates Neuromorphics cmos technology Circuit faults logic devices Fault tolerant systems Design methodology Very large scale integration

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A 3$\,\times\,$5-Gb/s Multilane Low-Power 0.18-$\mu{\hbox {m}}$ cmos Pseudorandom Bit Sequence Generator

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IEEE Transactions on circuits and Systems II: Express Briefs 2008年第5期55卷 432-436页

作者： Kin-Joe Sham Shubha Bommalingaiahnapallya Mahmoud Reza Ahmadi Ramesh Harjani Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA

A low-power, three-lane, pseudorandom bit sequence (PRBS) generator has been fabricated in a 0.18-mum cmos process to test a multilane multi-Gb/s transmitter that cancels far-end crosstalk. Although the proposed PRBS generator was designed to produce three uncorrelated 12-Gb/s PRBS sequences, measurement results included in this paper have been obtained at only 5 Gb/s due to test setup limitations. The prototype employs a cmos latch optimized to operate at frequencies close to the of the process and a current-mode logic (CML) MUX with modified active inductor loads for better high-speed large-signal behavior. In order to reduce the power consumption, a quarter-clock rate linear feedback shift register (LFSR) core in a power-efficient parallel architecture has been implemented to minimize the use of power-hungry, high-speed circuitry. Further power reduction has been achieved through the clever partitioning of the system into static logic and CML. In addition, the prototype design produces three uncorrelated 12-Gb/s data streams from a single quarter-rate LFSR core, thereby amortizing the power across multiple channels which lowers the power per channel by 3 times. The total measured power consumption at 5 Gb/s is 131 mW per lane and the calculated figure of merit per lane is 0.84 pJ/bit, which is significantly better than previously published designs.

关键词： cmos process Testing Prototypes Energy consumption Transmitters Crosstalk Latches Frequency cmos logic circuits Active inductors

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A power-gating scheme for CAL circuits using single-phase power-clock

A power-gating scheme for CAL circuits using single-phase po...

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IEEE Asia-Pacific Conference on circuits and Systems

作者： Weiqiang Zhang Li Su Jinghong Fu Jianping Hu Faculty of Information Science and Technology Ningbo University Ningbo Zhejiang China

This paper presents a power-gating scheme for CAL (clocked adiabatic logic) circuits to reduce energy loss during idle state. A transmission gate is used as the power-gating switch. It is inserted between the single-phase power-clock and virtual power-clocks to detach power-gated CAL logic blocks during idle periods. The 8-bit full adders based on the CAL circuits are used to verify the proposed power-gating technique. All circuits are simulated using the BSIM3V3 models of TSMC 0.18 mum cmos technology. Energy loss can be reduced greatly by shutting down idle adiabatic logic blocks.

关键词： Clocks logic circuits Switches Energy loss cmos logic circuits cmos technology MOSFETs Voltage Adders Circuit simulation

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A novel, highly SEU tolerant digital circuit design approach

A novel, highly SEU tolerant digital circuit design approach

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IEEE International Conference on Computer Design: VLSI in Computers and Processors, (ICCD)

作者： Rajesh Garg Sunil P. Khatri Department of ECE Texas A and M University College Station TX USA

In this paper, we present a new radiation tolerant cmos standard cell library, and demonstrate its effectiveness in implementing radiation hardened digital circuits. We exploit the fact that if a gate is implemented using only PMOS (NMOS) transistors then a radiation particle strike can result only in logic a 0 to 1 (1 to 0) flip. Based on this observation, we derive our radiation hardened gates from regular static cmos gates. In particular, we separate the PMOS and NMOS devices, and split the gate output into two signals. One of these outputs of our radiation tolerant gate is generated using PMOS transistors, and it drives other PMOS transistors (only) in its fanout. Similarly, the other output (generated from NMOS transistors) drives only other NMOS transistors in its fanout. Now, if a radiation particle strikes one of the outputs of the radiation tolerant gate, then the gates in the fanout enter a high-impedance state, and hence preserve their output values. Our radiation hardened gates exhibit an extremely high degree of SEU tolerance, which is validated at the circuit level. Using these gates, we also implement circuit level hardening based on logical masking, to selectively harden those gates in a circuit which contribute most to the soft error failure of the circuit. The gates with a low probability of logical masking are replaced by SEU tolerant gates from our new library, such that the digital design achieves a 90% soft error rate reduction. Experimental results demonstrate that this reduction is achieved with a modest layout area and delay penalty of 62% and 29% respectively, for area mapped designs. In contrast with existing approaches, our approach results in SEU immunity for extremely large critical charge values (>650fC).

关键词： Digital circuits Radiation hardening MOSFETs Software libraries MOS devices cmos digital integrated circuits cmos logic circuits logic devices Error analysis Delay

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