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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是601-610 订阅

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Low-voltage limitations and challenges of memory-rich nano-scale cmos LSIs

Low-voltage limitations and challenges of memory-rich nano-s...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Kiyoo Itoh Central Research Laboratory Hitachi Ltd. Tokyo Japan

ISBN: (纸本)9781424421855

The minimum operating voltage (V min ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V min that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V T ) of MOSFETs. The V min , however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k bulk) that can reduce V T variations.

关键词： Random access memory MOSFETs Read-write memory cmos logic circuits logic circuits logic gates logic devices Threshold voltage Flip-flops RNA

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cmos Adiabatic Driver with Bootstrap Technique for Driving Large Capacitive Loads

CMOS Adiabatic Driver with Bootstrap Technique for Driving L...

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International Symposium on Communications and Information Technologies (ISCIT)

作者： Jose C. Garcia Juan A. Montiel-Nelson Saeid Nooshabadi Institute for Applied Microelectronics University of Las Palmas Las Palmas Spain Department of Information and Communication Gwangju Institute of Science and Technology South Korea

This paper presents the design of a highly energy efficient cmos adiabatic driver (ee-driver). The proposed ee-driver uses an output stage with two bootstrap capacitors driven by a pre-driver circuit consisting of two differential cascode voltage switch (DCVS) logic cells. When implemented on a 0.13 mum cmos 1.2 V technology, under the large capacitive loading condition, ee-driver performs better than the reference adiabatic circuit (ab-driver) in terms of propagation delay (39%), the energy-delay product (39%), and active area (57%).

关键词： Driver circuits Switches cmos technology Energy efficiency Switched capacitor circuits Voltage Switching circuits cmos logic circuits logic circuits Propagation delay

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A Novel Approach to Design BCD Adder and Carry Skip BCD Adder

A Novel Approach to Design BCD Adder and Carry Skip BCD Adde...

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International Conference on VLSI Design

作者： Ashis Kumer Biswas Md. Mahmudul Hasan Moshaddek Hasan Ahsan Raja Chowdhury Hafiz Md. Hasan Babu Department of Computer Science and Engineering University of Dhaka Dhaka Bangladesh

ISBN: (纸本)9780769530833;0769530834

Reversible logic has become one of the most promising research areas in the past few decades and has found its applications in several technologies; such as low power cmos, nanocomputing and optical computing. This paper presents improved and efficient reversible logic implementations for Binary Coded Decimal (BCD) adder as well as Carry Skip BCD adder. It has been shown that the modified designs outperform the existing ones in terms of number of gates, number of garbage output and delay.

关键词： Adders Delay Optical computing DH-HEMTs cmos logic circuits logic circuits Energy loss Physics computing Temperature Quantum computing

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Decomposition based approach for synthesis of multi-level threshold logic circuits

Decomposition based approach for synthesis of multi-level th...

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Asia and South Pacific Design Automation Conference

作者： Tejaswi Gowda Sarma Vrudhula Consortium of Embedded Systems School of Computing and Informatics Arizona State University Tempe AZ USA

ISBN: (纸本)9781424419210

Scaling is currently the most popular technique used to improve performance metrics of cmos circuits. This cannot go on forever because the properties that are responsible for the functioning of MOSFETs no longer hold in nano dimensions. Recent research into nano devices has shown that nano devices can be an alternative to cmos when scaling of cmos becomes infeasible in the near future. This is motivating the need for stable and mature design automation techniques for threshold logic since it is the design abstraction used for most nano- devices. This paper presents a new decomposition theory that is based on the properties of threshold functions. The main contributions of this paper are: (1) A new method of algebraic factorization called the min-max factorization. (2) A decomposition theory that uses this new factorization to identify and characterize threshold functions. (3) A new threshold logic synthesis methodology that uses the decomposition theory. This synthesis methodology produces circuits that are better than the previous state of art (27% better gate count and comparable circuit depth).

关键词： Circuit synthesis logic circuits Measurement MOSFETs Design automation cmos logic circuits logic devices logic design Nanoscale devices logic functions

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Reconfiguring cmos as Pseudo N/PMOS for Defect Tolerance in Nano-Scale cmos

Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in ...

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International Conference on VLSI Design

作者： Maryam Ashouei Adit D. Singh Abhijit Chatterjee Georgia Institute of Technology USA Aubum University USA

ISBN: (纸本)9780769530833;0769530834

End-of-the-roadmap nanoscale cmos is expected to suffer from significant defectivity due to manufacturing defects, random process variations, and wear-out during normal operational. To ensure acceptable yield and reliable operation of the circuit during its life-time, future circuits must be equipped with significant defect-tolerance capabilities. Traditional defect-tolerance approaches are too expensive to be applied to general purpose circuits. In this paper, we propose a defect-tolerant cmos logic gate architecture that exploits the inherent functional redundancy in static cmos. This is accomplished by reconfiguring the cmos logic gate to a pseudo-NMOS-like gate in the presence of a defect. The resulting defect-tolerant logic architecture incurs only a modest area overhead. The proposed gate design can tolerate defects in either the pull-up or pull-down network of the gate. The architecture can tolerate multiple defects across the logic gates of a cmos logic circuit. The effectiveness of the proposed defect tolerance technique and its impact on circuit delay and power is studied. It is shown that the technique imposes little delay overhead (less than 6%) but incurs power dissipation overhead (less than 20%) in the presence of defects.

关键词： cmos logic circuits cmos technology logic gates Reconfigurable logic Circuit faults cmos process Redundancy Delay Circuit simulation Very large scale integration

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A novel cmos switched-current mode sequential shift forward inference circuit for fuzzy logic controller

A novel CMOS switched-current mode sequential shift forward ...

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IEEE Asia-Pacific Conference on circuits and Systems

作者： Ngai Kong Seng-Pan U R.P. Martins FST University of Macau Macao China Chipidea Microelectronics (Macao) Ltd. Portugal Instituto Superior Técnico/UTL Lisbon Portugal

A novel switched-current (SI) mode sequential shift forward inference circuit for a fuzzy logic controller (FLC) is presented. The cumulative error in each inference cycle is effectively cancelled in comparison with the previous architecture. SI basic cells are employed for high-frequency and low-voltage operation. The sequential structure ensures a low-power and compact realization whereas the digital portion is fully programmable. The analog input signal is processed directly without the need of an A/D or D/A interface. SPECTRE simulation results validate the feasibility of the proposed controller that is implemented in 0.35-mum cmos with a battery 1.5-V supply.

关键词： cmos logic circuits Switching circuits Fuzzy logic Fuzzy systems Inference algorithms Fuzzy sets Bismuth cmos technology Current mode circuits Batteries

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Calculation methods of new circuit activity measure for low power modeling

Calculation methods of new circuit activity measure for low ...

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International Conference on Signals and Electronic Systems, ICSES

作者： Ireneusz Brzozowski Andrzej Kos Department of Electronics AGH University of Science and Technology Cracow Poland

Calculation procedures for the gate driving way probability - the new measure of a circuit activity, developed for low power modeling - are presented in this paper. The new model of power dissipation, using the measure, has improved estimation accuracy. Moreover, it allows developing of new methods for low power design. The gate driving way can be easy calculated using logic simulations, but it is time-consuming method. So, the authors propose efficient and fast calculation procedures. The versatile algorithm for any circuit has been developed as well as very fast one for two-level circuits only. Results of new algorithms using were compared for a set of MCNC benchmark circuits.

关键词： Power measurement Capacitance Power dissipation Semiconductor device modeling Energy consumption cmos logic circuits Clocks Capacitors Circuit simulation Frequency

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A 1.6mm2 4,096 logic elements multi-context FPGA core in 90nm cmos

A 1.6mm2 4,096 logic elements multi-context FPGA core in 90n...

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IEEE Asian Conference on Solid-State circuits (ASSCC)

作者： Naoto Miyamoto Tadahiro Ohmi New Industry Creation Hatchery Center University of Tohoku Sendai Japan

In this paper, we propose a dynamically reconfigurable multi-context FPGA core named Flexible Processor IV (FP4). FP4 contains 16 times 16 physical logic elements (LE) and 16 context memory planes, thus virtually 4,096 LEs are available in total. The core size is only 1.36 mm times 1.15 mm in 90 nm cmos technology. A critical issue of FP4 is to prevent the fall of multi-context execution speed. Therefore we have developed a shift-register-type temporal communication module (SR-TCM) and a design automation software named PELOC. PELOC can divide a circuit larger than the physical capacity of FP4 to several smaller sub-circuits while maintaining critical path delay equal among all the sub-circuits. By using the SR-TCM and PELOC, we confirmed that the execution speed of FP4 is almost constant regardless of the number of contexts used.

关键词： Field programmable gate arrays Integrated circuit interconnections Delay effects cmos logic circuits Reconfigurable logic cmos technology Context Switches Added delay Communication switching

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Multiple Valued logic Using 3-State Quantum Dot Gate FETs

Multiple Valued Logic Using 3-State Quantum Dot Gate FETs

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International Symposium on Multiple-Valued logic

作者： John A. Chandy Faquir C. Jain Department of Electrical and Computer Engineering University of Connecticut USA

This paper presents fundamental logic structures designed using novel quantum dot gate FETs with three-state characteristics. This three-state FET manifests itself as a transistor with a stable "intermediate" state, where the drain current remains constant over a range of input gate voltages due to a change in the threshold voltage over this range. We have developed a simplified circuit model that accounts for this intermediate state. Using this model, we have designed rudimentary logic circuits for use in multiple-valued logic circuits.

关键词： Multivalued logic Quantum dots FETs Threshold voltage cmos logic circuits Insulation Quantum computing logic design logic circuits Tunneling

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A fully integrated cmos bio-chip aiming at selective assembly of charged nano-particles

A fully integrated CMOS bio-chip aiming at selective assembl...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Lei Zhang Yu Chang Zhiping Yu Xiangqing He Yong Chen Institute of Microelectronics Tsinghua University Beijing China Department of Mechanical and AeroSpace Engineering University of California Los Angeles USA

ISBN: (纸本)9781424421855

A fully integrated bio-chip targeting at electrical selective assembly of charged nano-particles is proposed and designed in SMIC 0.18 ¿m cmos mixed signal process. The proposed circuit integrates the electrode array, potentiostat circuit, and logics on a single chip, and provides a rail-to-rail range of assembly voltage, a potential resolution of 9 bit, and a maximal assembly current up to 0.46 mA, biased at a current of 1 ¿A. Meanwhile, a novel electrode-reuse scheme is also proposed to further simplify the architecture and save chip area as well, without degrading the functionalities. Experimental results from on-chip selective assembly of 50 nm poly-styrene nano-particles (PS) are included and discussed to verify the feasibility of the proposed circuits.

关键词： Assembly logic arrays Signal design cmos process Signal processing Electrodes cmos logic circuits logic circuits Voltage Signal resolution

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