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检索条件"主题词=CMOS Logic Circuits"

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High Electron Mobility (2270 cm2/Vsec) In0.53Ga0.47As Inversion Channel N-MOSFETs with ALD ZrO2 Gate Oxide Providing 1 nm EOT

High Electron Mobility (2270 cm2/Vsec) In0.53Ga0.47As Invers...

引用

Device Research Conference

作者： S. Koveshnikov N. Goel P. Majhi C. K. Gaspe M. B. Santos S. Oktyabrsky V. Tokranov M. Yakimov R. Kambhampati H. Bakhru F. Zhu J. Lee W. Tsai University at Albany SUNY NY Intel Intel Corporation Santa Clara CA Intel Intel Corporation Santa Clara CA USA SEMATECH Austin TX USA The University of Oklahoma Norman USA University at Albany SUNY NY USA University of Texas at Austin Austin TX USA

Self-aligned MOSFETs with high-Indium content InGaAs based channel, ultra-thin high-k dielectric and metal gate are attractive devices for logic applications. To be compatible with the future generation cmos technology, these devices must demonstrate high channel mobility and excellent performance at low operating voltage. Development of a thermally stable I-V/high-k interface with low EOT and low interface state density remains the key challenge for compound semiconductor implementation.

关键词： Electron mobility High-K gate dielectrics cmos technology MOSFETs Indium gallium arsenide cmos logic circuits logic devices Low voltage High K dielectric materials Interface states

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High-speed serial interconnect transceiver: Applications and design

High-speed serial interconnect transceiver: Applications and...

引用

IEEE Asia-Pacific Conference on circuits and Systems

作者： Hui Wang Yuhua Cheng Shanghai Research Institute of MicroElectronics(SHRIME) Peking University Shanghai China

In this paper, the design and applications of high-speed interconnect transceivers are presented. Serial interconnect transceivers have been widely adopted for its high data transfer rate, low cost, good noise immunity and low EMI. Signal SNR can be severely degraded by transmission channel. Channel modeling and analysis are very critical in high-speed serial transceiver design. Effects due to channel impairments and tradeoffs among different equalization techniques are discussed in the paper. Implementation examples of key building blocks for high-speed serial transceiver in deep sub-micron cmos logic process are also introduced.

关键词： Transceivers Integrated circuit interconnections Degradation cmos process cmos logic circuits Clocks cmos technology Bandwidth Costs Application specific integrated circuits

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Low-power high-performance logic style for low-voltage cmos technologies

Low-power high-performance logic style for low-voltage CMOS ...

引用

International Conference on Microelectronics, ICM

作者： Bardia Bozorgzadeh Ehsan Zhian-Tabasy Ali Afzali-Kusha Nanoelectronics Center of Excellence School of Electrical and Computer Engineering University of Tehran Tehran Iran

In this paper, a low-power high-performance logic style for low-voltage cmos technologies is presented. The style is based on modifying a high-speed yet low-power logic family called feedthrough logic (FTL) style which has been previously proposed in the literature. The proposed style which is called parallel FTL (PFTL) overcomes the shortcoming of the FTL for low-voltage applications. To assess the efficiency of the proposed logic style, HSPICE simulations are used to compare the performance parameters of PFTL, FTL, and static cmos logic. The simulation results in 45 nm standard cmos show a superiority of the proposed structure, especially at low supply voltages. The PFTL has reduced the delay over the standard cmos logic by 12 to 16 times and over the FTL structure by 3 times, and also PFTL has reduced (delay × power/frequency) ratio over the FTL by 3.5 times and over the standard cmos by 30 percent at low supply voltages.

关键词： cmos technology cmos logic circuits Low voltage Variable structure systems logic gates Clocks Propagation delay MOS devices Switches Microelectronics

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New D-Type Flip-Flop Design Using Negative Differential Resistance circuits

New D-Type Flip-Flop Design Using Negative Differential Resi...

引用

IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： Dong-Shong Liang Kwang-Jow Gan Department of Electronic Engineering and Nano Technology Research and Development Centre Kun Shan University Tainan Taiwan

A novel D-type flip-flop designed using negative differential resistance (NDR) circuit based on standard 0.35 mum cmos process is demonstrated. First we propose a new NDR circuit that is made of metal-oxide- semiconductor field-effect-transistor (MOS), but it can show the NDR characteristic in its current-voltage curve by suitably designing the MOS widths/lengths parameters. The flip-flop circuit is composed by two monostable and one monostable-bistable transition logic elements (MOBILE). The performance of these circuits is evaluated by using HSPICE.

关键词： Flip-flops Voltage MOS devices Circuit testing Circuit simulation Electronic equipment testing cmos process cmos logic circuits logic devices System-on-a-chip

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A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm cmos

A 32mW 1.25GS/s 6b 2b/step SAR ADC in 0.13μm CMOS

引用

IEEE International Conference on Solid-State circuits (ISSCC)

作者： Zhiheng Cao Shouli Yan Yunchu Li University of Texas at Austin Austin TX Austin Analog Devices Wilmington MA USA

ADCs with 6b resolution and gigahertz sampling frequency are widely used in serial links, magnetic recording systems and UWB receivers. Flash ADCs have been dominantly used for these applications. This paper presents an ADC that takes advantage of the high-speed digital logic and highly matched small capacitors in deep-submicron digital cmos processes to achieve similar performance, but with lower power consumption than flash ADCs. Unlike many previously published low-power high-speed ADCs based on time-interleaved SAR, this ADC has only 2 clock-cycle latency (1.6ns at 1.25GS/s) and achieves 6b performance without any digital post-processing or off-line calibration, making it a plug- in replacement for conventional flash ADCs in many applications.

关键词： Sampling methods Frequency Magnetic recording cmos logic circuits Capacitors cmos process Energy consumption Clocks Delay Calibration

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Performance comparison of static cmos and MCML gates in sub-threshold region of operation for 32nm cmos technology

Performance comparison of static CMOS and MCML gates in sub-...

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International Conference on Computer and Communication Engineering, ICCCE

作者： Tarun Kumar Agarwal Anurag Sawhney A.K. Kureshi Mohd. Hasan Department of Electronics Engineering Aligarh Muslim University Aligarh India Department of Electronics Engineering Zakir Hussain College of Engineering and Technology Aligarh Muslim University India

This paper investigates the performance of static cmos logic circuits and MOS current mode logic (MCML) circuits in sub-threshold region. The simulations are based on 32 nm Berkeley predictive technology model (BPTM) running in HSPICE software. It is found that MCML logic circuits exhibit a decrease in delay and so decrease in overall PDP, which is one of our performance measures, with scaling of input voltage which is contrary to the behavior of static cmos logic circuits. The results show a propagation delay improvement of more than 10 times when using MCML logic over cmos logic in sub-threshold region of operation. Further the performance in terms of PDP of MCML logic circuits is improved by a factor of 7-10 when the input voltage is scaled down from 0.4 V to 0.2 V. .The results of various circuit simulations have been illustrated and compared by defining certain performance measures and the trade off between these performance measures.

关键词： cmos technology cmos logic circuits logic circuits Voltage control Crosstalk Inverters Predictive models Circuit simulation Delay logic devices

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A low power high speed ROIC design for 1024×1024 IRFPA with novel readout stage

A low power high speed ROIC design for 1024×1024 IRFPA with...

引用

IEEE Conference on Electron Devices and Solid-State circuits

作者： Chang Liu Wengao Lu Zhongjian Chen Haimei Bian Lijiu Ji Key Laboratory of Microelectronic Devices and Circuits Institute of Microelectronics Peking University

A low power high speed Read-Out Integrated Circuit (ROIC) for a short-wave Infra-Red Focal Plane Array (IRFPA) is designed as a prototype for 1024 times 1024 image system. Ripple integration and readout scheme as well as highly efficient power management are introduced to this design in order to decrease total power. To further increase the readout speed while decrease the power dissipation, a novel readout stage is proposed and adopted in this circuit. By using the new structure, the ROIC achieves a data rate of 10 M/s per channel, with the total power dissipation of 56 mW.

关键词： Power dissipation cmos logic circuits logic arrays Detectors Capacitors Power amplifiers Prototypes logic devices Cooling Timing

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Full Open Defects in Nanometric cmos

Full Open Defects in Nanometric CMOS

引用

26th IEEE VLSI Test Symposium (VTS 2008)

作者： D. Arumi R. Rodriguez-Montanes J. Figueras S. Eichenberger C. Hora B. Kruseman Departament d'Enginyeria Electrònica Universitat Politècnica de Catalunya Barcelona SPAIN NXP Semiconductors THE NETHERLANDS

Full open defects on the interconnect lines cause the broken wires to become floating. The voltage of a floating line depends on its topological characteristics, namely: parasitic capacitances to neighbouring structures, transistor capacitances of the downstream gate(s) and the trapped charge. However, in nanometric cmos technologies, the oxide thickness is reduced below a few tens of A causing the gate tunnelling leakage to strongly impact the behaviour of defective circuits with full open defects. Floating lines can not be considered electrically isolated anymore and are subjected to transient evolutions until arriving at a quiescent state, determined by the technology and the downstream gate(s). The occurrence of full opens as well as the impact of the gate tunnelling leakage is expected to increase for future technologies. The analysis of full opens affecting basic cmos gates is presented and their defective behaviour characterized. The prediction of the defective logic response of such basic gates is presented for nanometric technologies based on Predictive Technology Models. The final steady state is found to be independent on the initial state of the floating node. Experimental evidence of this behaviour is presented for an industrial chip of 0.18μm technology.

关键词： cmos technology Isolation technology Parasitic capacitance Tunneling Integrated circuit interconnections Wires Voltage Capacitance-voltage characteristics cmos logic circuits Semiconductor device modeling

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Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

Migration of Cell Broadband Engine from 65nm SOI to 45nm SOI

引用

IEEE International Conference on Solid-State circuits (ISSCC)

作者： O. Takahashi C. Adams D. Ault E. Behnen O. Chiang S. R. Cottier P. Coulman J. Culp G. Gervais M. S. Gray Y. Itaka C. J. Johnson F. Kono L. Maurice K. W. McCullen L. Nguyen Y. Nishino H. Noro J. Pille M. Riley M. Shen C. Takano S. Tokito T. Wagner H. Yoshihara IBM Austin TX USA IBM Rochester MN USA IBM Hopewell Junction NY USA IBM Essex Junction VT USA Toshiba America Electronics Components Inc. Austin TX USA Sony Computer Entertainment America Austin TX USA IBM Boeblingen Germany

ISBN: (纸本)9781424420100

This paper describe the challenges of migrating the Cell Broadband Engine (Cell BE) design from a 65 nm SOI to a 45 nm twin-well cmos technology on SOI with low-k dielectrics and copper metal layers using a mostly automated approach. A die micrograph of the 45 nm Cell BE is described here. The cycle-by-cycle machine behavior is preserved. The focuses are automated migration, power reduction, area reduction, and DFM improvements. The chip power is reduced by roughly 40% and the chip area is reduced by 34%.

关键词： Engines Frequency Power supplies cmos logic circuits Programmable logic arrays Delay Timing Power measurement Semiconductor device measurement Predictive models

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Post cmos Nanoelectronics Research for the Next Generation logic Switches

Post CMOS Nanoelectronics Research for the Next Generation L...

引用

International Symposium on VLSI Technology, Systems and Applications

作者： C.Y. Sung IBM Research Division T.J. Watson Research Center Institute for Nanoelectronics Discovery and Exploration Center Yorktown Heights NY USA

ISBN: (纸本)9781424416141

Electron charge has been the computational state variable for decades. The industry has benefited by scaling charge-based devices to provide better performance per unit cost. However, a new switch is urgently needed because scaling may fail to keep providing benefits at the historical rate. We discuss charge switch thermal dissipation limits, the nanoelectronics research initiative (NRI) effort, and emerging technologies in this paper.

关键词： Nanoelectronics cmos logic circuits Switches cmos technology logic devices Thermodynamics Throughput Electron tubes Thermal management Temperature

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