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检索条件"主题词=CMOS Logic Circuits"

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Design and performance analysis of one 32-bit dual issue RISC processor for embedded application

Design and performance analysis of one 32-bit dual issue RIS...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Xiaoping Huang Xiaoya Fan Shengbing Zhang Northwestern Polytechnical University Xi'an China

ISBN: (纸本)9781424421855

One 32-bit RISC processor for embedded application is presented. With respect to the limitation of power and area in the embedded system, the RISC processor is deliberately designed. Dual-issue technology is adopted to improve the performance; the complex logic of the dynamic scheduling algorithm is allocated into different pipeline stage to improve the frequency. Lower power design method is used to decrease the whole power. The processor is implemented by SMIC 0.18 um cmos technology. It contains almost 5 million transistors; the core frequency is 266 MHz and the power is about 1.3 w under it. The embedded VxWorks OS can run on it stably. The performance analysis of the RISC processor is also provided. According to the embedded benchmark program, the average IPC of the RISC processor is nearly 1.5.

关键词： Performance analysis Reduced instruction set computing cmos technology Embedded system Process design cmos logic circuits Dynamic scheduling Heuristic algorithms Scheduling algorithm Pipelines

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Design of a low power binary counter using bistable storage element

Design of a low power binary counter using bistable storage ...

引用

International Conference on Electronic Design (ICED)

作者： Erastus Ogunti Michael Frank Simon Foo Department of Electrical & Computer Engineering FAMU FSU College of Engineering Tallahassee FL USA Frank Enterprises Limited Liability Company Tallahassee FL USA

An architecture for a O(1)-loss irreversible n-bit counter is presented in this paper. It is presented as an initial stepping stone application that is suitable for clarifying the potential energy-efficiency advantages of reversible computing. It is based on using fairly standard, irreversible, semi-static cmos logic. Care is taken to ensure that energy is not dissipated at subsequent counter bits, except those that are actually changing values on a given cycle. The design utilizes two-phase non-overlapping clocks, phi 0 and phi 1 with fast rise and fall times. For high system level energy-efficiency, the clocks were generated resonantly using the rotary clock scheme. XOR gates serve as phase detectors with AND gates helping to maintain parity checking. Transmission gates ensure a semi-static logic since the logic levels are restored only during the high portion of the clock period. We compared the power dissipation of an 8-bit counter designed using this logic to a standard 8-bit binary counter design using flip-flops in the 50 nm process and recorded a power advantage of about 60%. A prototype will be sent to MOSIS for fabrication to confirm energy advantage of this design after testing.

关键词： Counting circuits Clocks Energy efficiency Computer architecture cmos logic circuits Resonance Phase detection Detectors Power system restoration Power dissipation

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High-Level Design of Multiple-Valued Arithmetic circuits Based on Arithmetic Description Language

High-Level Design of Multiple-Valued Arithmetic Circuits Bas...

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International Symposium on Multiple-Valued logic

作者： Yuki Watanabe Naofumi Homma Katsuhiko Degawa Takafumi Aoki Tatsuo Higuchi Graduate School of Information Sciences University of Tohoku Sendai Japan ADVANTEST Corporation Gunma Japan Department of Electronics Tohoku Institute of Technology Sendai Japan

This paper proposes a high-level design method of multiple-valued arithmetic circuits. The proposed method uses a cell-based approach with a dedicated hardware description language called ARITH. By using ARITH, we can describe and verify any binary/multiple-valued arithmetic circuits in a formal manner. The ARITH description can be transformed into a technology-dependent netlist in binary/multiple-valued fused logic. The process of transforming the netlist into a physical layout pattern is automatically performed by an off-the-shelfplace-and-route tool. In this paper, we present a specific cell library containing a multiple-valued signed-digit adder and its related circuits with a 0.35mum cmos technology, and demonstrate that the proposed method can synthesize a 32times 32-bit parallel multiplier in multiple-valued current-mode logic from an ARITH description.

关键词： Signal processing algorithms cmos logic circuits cmos technology Design methodology Hardware design languages Adders Circuit synthesis Algorithm design and analysis Digital arithmetic Multivalued logic

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Pure logic cmos based embedded Non-Volatile Random Access Memory for low power RFID application

Pure logic CMOS based embedded Non-Volatile Random Access Me...

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Custom Integrated circuits Conference (CICC)

作者： Liyang Pan Xian Luo Yaru Yan Jirong Ma Dong Wu Jun Xu Institute of Microelectronics Tsinghua University Beijing China Tsinghua National Laboratory for Information Science and Technology China

Based on a novel two-dimension array architecture, a 1.8 V 0.44 mm 2 1 Kbits embedded non-volatile random access memory (NVRAM) IP is developed with 0.18 mum standard logic cmos process. Several high voltage solutions and circuits are proposed to improve the reliability and safety of the system. Furthermore, the power consumption for read and write operations are controlled under 312 muA and 88 muA respectively. The merits make it suitable for low power RFID application.

关键词： cmos logic circuits Nonvolatile memory Random access memory Radiofrequency identification logic arrays Standards development cmos process Voltage Power system reliability Safety

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Neutron and alpha particle-induced transients in 90 nm technology

Neutron and alpha particle-induced transients in 90 nm techn...

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Annual International Symposium on Reliability Physics

作者： Balaji Narasimham Matthew J. Gadlage Bharat L. Bhuva Ronald D. Schrimpf Lloyd W. Massengill W. Timothy Holman Arthur F. Witulski Xiaowei Zhu Anupama Balasubramanian Steve A. Wender Department of EECS Vanderbilt University Nashville TN USA Texas Instruments Inc. Dallas TX USA Department of EECS Los Alamos National Laboratory Los Alamos NM USA

Combinational logic soft errors are a major environment-related reliability issue in advanced cmos processes. The key to determining logic soft error rates (SER) is detailed knowledge of neutron and alpha particle-induced single event transient (SET) pulse widths, but these pulse widths have not been measured previously. experimental results obtained using a novel test chip fabricated in a 90 -nm cmos technology indicate the SET widths are similar to those of legitimate logic signals.

关键词： Neutrons cmos technology cmos logic circuits logic testing Pulse measurements Space vector pulse width modulation cmos process Error analysis Particle measurements Semiconductor device measurement

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Innovations to extend cmos nano-transistors to the limit 08

Innovations to extend CMOS nano-transistors to the limit

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Tahir Ghani Intel Corporation Hillsboro Oregon USA

ISBN: (纸本)9781605581095

Summary form only given. The scaling of cmos technology has led to phenomenal growth in transistor density and performance during the last three decades. However, starting at 90nm cmos node, the industry started to experience significant barriers in achieving historical transistor performance gains through traditional dimensional scaling. Fortunately, the industry has responded positively to this challenge by implementing many innovations in device structure and materials to overcome traditional scaling barriers. Intel has been at the forefront in addressing these challenges by successfully driving transistor innovations from research phase to mainstream cmos manufacturing. Implementation of uniaxial strained-silicon transistors at the 90nm node and the recently announced "HiK+Metal Gate" transistors for the 45nm node are two excellent examples of major innovations which have demonstrated dramatic performance enhancement. After a brief review highlighting the dramatic performance benefits demonstrated with uniaxial strained silicon technology, I will describe process details and present significant performance gains achieved with "HiK+Metal Gate" transistor technology for 45nm cmos node. Finally, I will discuss the role of increasing power density and transistor parasitics in limiting future cmos transistor scaling and describe potential new transistor structure and material innovations required to meet performance/power/density improvements beyond 45nm cmos node. The convergence of new transistor structure and materials will be critical for successfully scaling cmos transistors through next decade.

关键词： Technological innovation cmos technology cmos logic circuits Manufacturing industries Silicon Performance gain Biological materials cmos process Integrated circuit reliability Electronics industry

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Power-gating-aware high-level synthesis

Power-gating-aware high-level synthesis

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Eunjoo Choi Changsik Shin Taewhan Kim Youngsoo Shin System IC Busin-ess Team LG Electronics Seoul Korea Departrnent of Electrical Engineerinq KAIST Daejeon Korea Department of Electrical Engineering Seoul National University Seoul Korea

A problem inherent in designing power-gated circuits is the overhead of the state-retention storage required to preserve the circuit state in standby mode. Reducing the amount of retention storage is known to be the most influential factor in minimizing the loss of the benefit (i.e. power saving) by power-gating. In this paper, we address a new problem of high-level synthesis with the objective of minimizing the size of retention storage to be used in the power-gated circuits. Specifically, we propose a complete design framework, called HLS-pg, that starts from the power-gating-aware scheduling, allocation, and controller synthesis down to the final circuit layout. The key contribution of the work is to solve the power-gating-aware scheduling problem, namely, scheduling operations that minimizes the number of retention registers required at the power-gating control step, while satisfying resource and latency constraints. In experiments on benchmark designs implemented in 65-nm cmos technology, HLS-pg generates circuits with 27% less leakage current, with 6% less circuit area and wirelength, compared to the power-gated circuits produced by conventional high-level synthesis.

关键词： High level synthesis cmos technology Leakage current Circuit synthesis Latches Flip-flops Registers Integrated circuit synthesis cmos logic circuits logic design

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A 43-GHZ static frequency divider in 0.13μM standard cmos

A 43-GHZ static frequency divider in 0.13μM standard CMOS

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Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Bangli Liang Dianyong Chen Bo Wang Dezhong Cheng Tad Kwasniewski Department of Electronics Carleton University Ottawa ONT Canada

In this paper, a low supply static 2:1 frequency divider based on 0.13 mum cmos is presented. It is designed for 40-Gb/s optical communication systems. Current-mode logic (CML) is adopted because of the higher speed compared to static cmos and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors and split-resistor (SR) loads are used to boost the bandwidth. The frequency divider uses a single 1.2-V supply voltage and consumes a total current of 32 mA. And the chip area is only 0.63 mm 2 with bonding pads.

关键词： Frequency conversion Optical frequency conversion Optical design Optical fiber communication cmos logic circuits Robustness Optical buffering Shunt (electrical) Inductors Strontium

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A power, performance scalable eight-cores media processor for mobile multimedia applications

A power, performance scalable eight-cores media processor fo...

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IEEE Asian Conference on Solid-State circuits (ASSCC)

作者： Yasuyuki Ueda Nobuhiro Nonogaki Toshihiro Terazawa Takeshi Kodaka Takayuki Mori Kumiko Morita Hideho Arakida Takashi Miura Yukimasa Miyamoto Yuji Okuda Toshiki Kizu Yoshiro Tsuboi Semiconductor Company Toshiba Corporation Kawasaki Japan Toshiba Microelectronics Center Kawasaki Japan

We have developed a parallel process execution scheme, which enables reusable software to achieve high performance scalability for mobile multimedia application in according to available resources. Also, performance scalability on an eight-cores media processor with low power circuits is certified by evaluating H.264 decoding. The high reusability of media processing engines and software developed on the basis of our scheme enable software solution to cover various image, media applications.

关键词： Application software Multicore processing Yarn Software performance Scalability cmos logic circuits Software reusability Decoding Engines Static VAr compensators

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Power analysis of resonant clocks

Power analysis of resonant clocks

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International Conference on Computer and Communication Engineering, ICCCE

作者： Erastus Ogunti Michael Frank Simon Y. Foo Department of Electrical and Computer Engineering FAMU and FSU College of Engineering Tallahassee FL USA Frank Enterprises LLC Tallahassee FL USA

Resonant clocks are new design techniques for multi-gigahertz clock distributions that are gaining prominence in the design of low power and ultrahigh frequency microprocessors. In the radiofrequency range, new challenges with respect to skews and jitters become greatly pronounced rendering many conventional clocking techniques inadequate. In this work, we present a comparative study of the power dissipation of three resonant clocking techniques: standing wave, rotary wave and dasiaresonant-loadpsila global clock distributions. Specifically, we generated non-overlapping clock signals resonantly to drive transmission gates in the design of our new binary counter. We used a simplified Sunpsilas SwaP Metric to determine the power efficiency of each resonant technique. All of our designs were simulated using Agilent ADS 2006A. Furthermore, our analysis has revealed that the rotary clock design can achieve a power efficiency of a magnitude of two compared to the other resonant clock techniques.

关键词： Resonance Clocks Power dissipation Counting circuits Costs Frequency cmos logic circuits Power transmission lines Oscillators Signal generators

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