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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是661-670 订阅

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A Process-Variation-Tolerant Floating-Point Unit with Voltage Interpolation and Variable Latency

A Process-Variation-Tolerant Floating-Point Unit with Voltag...

引用

IEEE International Conference on Solid-State circuits (ISSCC)

作者： Xiaoyao Liang David Brooks Gu-Yeon Wei Harvard University Cambridge MA USA

ISBN: (纸本)9781424420100

This paper explores two fine-grained, post-fabrication circuit-tuning techniques to combat process variation for pipelined logic componentsrdquo voltage interpolation and variable latency. These techniques are applied to a single-precision floating-point unit (FPU) designed using a standard CAD synthesis flow in a 0.13 mum cmos logic process with 8 metal layers. Measured results from fabricated chips show that both techniques provide wide frequency tuning range to deal with frequency fluctuations arising from process variations with minimal power overhead, and in some configurations, power savings.

关键词： Voltage Interpolation Delay cmos logic circuits Frequency logic circuits Design automation Circuit synthesis cmos process logic design

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A self-timing switch-driving register by precharge-evaluate logic for high-speed SAR ADCs

A self-timing switch-driving register by precharge-evaluate ...

引用

IEEE Asia-Pacific Conference on circuits and Systems

作者： U-Fat Chio He-Gong Wei Yan Zhu Sai-Weng Sin Seng-Pan U R.P. Martins Analog and Mixed Signal VLSI Laboratory Faculty of Science and Technology University of Macau Macao China

Novel self-timing switch-driving registers for high-speed successive approximation register (SAR) ADC is proposed. This circuit can provide fast charging path from comparator output to DAC array of SAR ADC and store the comparison results simultaneously at each approximation bit-cycle. The propagation delay from input to output of the register is about 60 ps only in a 90 nm cmos process. By using this technique, the 5-bit SAR ADC achieves 30.3 dB SNDR with 285 MS/s high sampling-rate, power consumption is 10.5 mW.

关键词： Propagation delay Capacitors Strontium Latches Voltage Shift registers Clocks Switching circuits logic circuits cmos logic circuits

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An Optimal Multi-Functional Unit Dynamic Instruction Selection logic at Submicron Technologies

An Optimal Multi-Functional Unit Dynamic Instruction Selecti...

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International Conference on VLSI Design

作者： Terrell Bennett Rama Sangireddy Department of Electrical Enginnering University of Texas Dallas Richardson TX USA

ISBN: (纸本)9780769530833;0769530834

As the technology scales, reduction in transistor size creates many opportunities for increased circuit capabilities in reduced chip area. In modern wide-issue processors, performance of the processor is directly impacted by the time delay complexity of the dynamic scheduling logic. In this paper, we analyze the scaling of time delay of instruction select logic at the submicron technologies, and also present novel designs that provide a single selection tree for two similar functional units. The designs are based on a tree structure using arbiter cells of two and four inputs which can handle one or two functional units. The effects of technology and design decisions are shown based on simulations using four submicron technologies. The delays in the select logic trees are shown to decrease by an average of 60% from 130 nm technology to 45 nm technology when servicing a single functional unit. The double grant arbiter cells are shown to build a tree that will serve multiple functional units simultaneously with 65% lesser delay as compared to multiple single-grant trees 1 .

关键词： logic design Dynamic scheduling Processor scheduling logic circuits Delay effects Frequency Out of order cmos logic circuits Very large scale integration Tree data structures

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Behavioral model of V and V+ gates to implement the reversible circuits using quantum gates

Behavioral model of V and V+ gates to implement the reversib...

引用

IEEE Region 10 International Conference TENCON

作者： Majid Mohammadi Mohammad Eshghi Abbas Bahrololoom Shahid Beheshti University Tehran Iran Shahid Beheshti University Kerman Iran

This paper addresses using quantum gates to implement binary reversible logic circuits. We propose behavioral models for well known V and V + quantum gates. Our proposed representation is used to synthesize reversible logic circuits instead of using the known unitary matrix form of quantum gates. This technique allows V and V + gates to be represented in truth table forms. Results show that our technique can be used to synthesize circuits with bigger sizes and gate counts in compare with unitary matrix form of these gates. Several reversible circuit benchmarks are optimized and compared to related works.

关键词： Circuit synthesis logic circuits Quantum computing cmos technology Quantum mechanics logic gates Space technology Circuit simulation cmos logic circuits Software algorithms

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A low-power programmable dynamic frequency divider

A low-power programmable dynamic frequency divider

引用

European Conference on Solid-State circuits (ESSCIRC)

作者： Jeremie Chabloz David Ruffieux Christian Enz Swiss Center for Electronics Microtechnology (CSEM) Neuchâtel Switzerland

In this paper, a solution to realize a low-power programmable frequency divider using dynamic logic is proposed. By cascading compact dual-modulus divider slice with recursive feedback mechanisms, any dividing ratio is easily implemented. A 5-stages 0.18 mum cmos implementation demonstrates a power consumption factor as low as 235 nW/MHz under 1.2 V supply for high dividing ratios.

关键词： Frequency conversion Phase locked loops Clocks Ring oscillators Frequency synthesizers cmos logic circuits Local oscillators Switches Injection-locked oscillators Feedback

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Leakage-based differential power analysis (LDPA) on sub-90nm cmos cryptosystems

Leakage-based differential power analysis (LDPA) on sub-90nm...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Lang Lin Wayne Burleson Department of Electrical and Computer Engineering University of Massachusetts Amherst Amherst MA USA

Since the vulnerability of cryptosystems to differential power analysis (DPA) was reported in 1999, various power analysis attacks and corresponding countermeasures have been studied. With the scaling down of supply voltage and cmos technology below 90 nm, leakage power plays an increasing role in the overall power dissipation. Future cryptosystems need to address this trend, though it has not been of concern yet in low- cost cryptosystems such as smartcards and RFED tags which currently use older technologies and low performance transistors. In this paper, we explore the impact of leakage power on conventional DPA and the feasibility of a novel leakage-based DPA (LDPA). We first use SPICE simulations to explore the leakage dependence on input patterns of logic gates implemented in 90 nm, 65 nm, and 45 nm cmos technologies. Then we simulate a successful LDPA on a subset of a DES cryptosystem with only 120 rounds, in contrast to the 200 rounds reported for a conventional DPA in 180 nm technology. Furthermore, we demonstrate how even a DES implementation using a DPA-resistant logic style can be broken with LDPA in 2000 rounds, compared with the conventional DPA using more than 5000 rounds.

关键词： Log-periodic dipole antennas Cryptography cmos technology cmos logic circuits Semiconductor device modeling Power dissipation RFID tags SPICE Switches Voltage

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A 3.6pW/frame·pixel 1.35V PWM cmos Imager with Dynamic Pixel Readout and no Static Bias Current

A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixe...

引用

IEEE International Conference on Solid-State circuits (ISSCC)

作者： Keiichiro Kagawa Sanshiro Shishido Masahiro Nunoshita Jun Ohta Osaka University Suita Japan Nara Institute of Science and Technology Ikoma Japan

ISBN: (纸本)9781424420100

Low-power operation of cmos imagers using a low voltage (around IV or less) compatible with deep submicron logic circuits enables new imager applications, such as disposable medical cameras and autonomous wireless security cameras on a chip. Pulse width modulation (PWM) is promising for this purpose. A PWM pixel can convert light intensity to a digital pulse width by using an in-pixel comparator with a low power-supply voltage without any degradation of signal-to-noise ratio (SNR). In this paper, we propose and demonstrate a low-power dynamic pixel readout in-pixel comparators(DPR) scheme with CGA PWM pixels based on dynamic operation of in-pixel comparators. DPR requires no static bias current even in the pixel readout. The power dissipation of the pixel array is dramatically reduced by 1 to 2 orders of magnitude compared with using normal static pixel readout (SPR).

关键词： Pulse width modulation Pixel Low voltage cmos image sensors Cameras Space vector pulse width modulation cmos logic circuits logic circuits Biomedical imaging Communication system security

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An embedded ultra low power nonvolatile memory in a standard cmos logic process

An embedded ultra low power nonvolatile memory in a standard...

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IEEE Conference on Electron Devices and Solid-State circuits

作者： Y-L. Li P. Feng N-J. Wu State Key Laboratory for Superlattices and Microstructures Institute of Semiconductors Chinese Academy and Sciences

This paper proposes an embedded ultra low power nonvolatile memory in a standard cmos logic process. The memory adopts a bit cell based on the differential floating gate PMOS structure and a novel operating scheme. It can greatly improve the endurance and retention characteristic and make the area/bit smaller. A new high efficiency all-PMOS charge pump is designed to reduce the power consumption and to increase the power efficiency. It eliminates the body effect and can generate higher output voltage than conventional structures for a same stage number. A 32-bit prototype chip is fabricated in a 0.18 mum 1P4M standard cmos logic process and the core area is 0.06 mm 2 . The measured results indicate that the typical write/erase time is 10 ms. With a 700 kHz clock frequency, power consumption of the whole memory is 2.3 muA for program and 1.2 muA for read at a 1.6 V power supply.

关键词： Nonvolatile memory cmos process cmos logic circuits Energy consumption Charge pumps Voltage Prototypes Semiconductor device measurement Time measurement Clocks

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Predicting common mode radiation of power bus structure excited by IC’s switching current

Predicting common mode radiation of power bus structure exci...

引用

International Zurich Symposium on Electromagnetic Compatibility (EMC Zurich)

作者： Toshio Sudo Shibaura Institute of Technology Koto Tokyo Japan

Predicting methods of common mode radiated emission of power bus structure have been investigated. Transient current flows at the power supply terminal was assumed to an exciting source, and the power bus consisted of power and ground planes was assumed to work as antenna of common mode radiation. Two simulation approaches were studied: one is a time-domain response-based approach, and another one was a frequency response-based approach. The test board consisted of 4 conductive layers was fabricated to verify simulation results. Then, transient power supply current of the IC was monitored, and far-field radiated emission was measured in an anechoic room. The simulation results obtained by both approaches showed a good agreement with the measurement results.

关键词： Power supplies cmos logic circuits Current supplies Electromagnetic radiation Circuit simulation Power measurement Electromagnetic transients Electromagnetic compatibility Monitoring Printed circuits

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Scaling of Stacked gate technology for embedded NVM

Scaling of Stacked gate technology for embedded NVM

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： D. Shum R. Kakoschke R. Strenz Infineon Technologies Dresden GmbH and Company OHG Germany Infineon Technologies Munich Germany

ISBN: (纸本)9781424421855

Scaling limitations on NVM Stacked gate embedded into high-performance (HP) cmos logic process will be reviewed with potential solutions identified. As technology continues its shrink path into 65 nm and beyond, scaling is becoming challenged due to the required high fields for write and erase (W/E) in stacked gate technology and the low leakage requirements for long term retention after cycling (RAC) problems. These requirements are imposing fundamental scaling limitations on the cell design as well as dielectrics thicknesses. These challenges require novel innovations to overcome and extend the viability of stacked gate technology to at least the 45 nm node.

关键词： cmos technology Nonvolatile memory Technological innovation Tunneling cmos logic circuits cmos process Dielectrics Voltage Costs Consumer electronics

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