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检索条件"主题词=CMOS Logic Circuits"

共 4527 条记录，以下是671-680 订阅

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Low Voltage Design against Power Analysis Attacks

Low Voltage Design against Power Analysis Attacks

引用

IEEE International Workshop on Electronic Design, Test and Applications (DELTA)

作者： O. Mirmotahari Y. Berg Microelectronic Systems (Mes) Department of Informatics University of Oslo Norway

In this paper we promote the ultra low voltage (ULV) gate to replace either partly or entirely the encryption block of a design to withstand power analysis attack. Some of the keywords in this work are: differential p... 详细信息

关键词： Low voltage Cryptography logic design cmos logic circuits Electronic equipment testing System testing Current supplies Security Application specific integrated circuits Smart cards

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A novel SPRAM (SPin-transfer torque RAM)-based reconfigurable logic block for 3D-stacked reconfigurable spin processor

A novel SPRAM (SPin-transfer torque RAM)-based reconfigurabl...

引用

International Electron Devices Meeting (IEDM)

作者： M. Sekikawa K. Kiyoyama H. Hasegawa K. Miura T. Fukushima S. Ikeda T. Tanaka H. Ohno M. Koyanagi Department of Bioengineering and Robotics Graduate School of Engineering University of Tohoku Sendai Japan Laboratory for Nanoelectronics and Spintronics Research Institute of Electrical Communication University of Tohoku Sendai Japan Advanced Research Laboratory Hitachi and Limited Sendai Japan

A novel reconfigurable logic block with SPRAM (spin-transfer torque RAM) is demonstrated. Magnetic elements of 50 times 200 nm 2 in area and cmos logic are fully integrated. Laboratory experimental results show that our reconfigurable logic block achieves 25 MHz read out operation with the magnetic resistance of 1.62 kOmega (parallel) and the MR ratio is 91.7 %.

关键词： Torque Reconfigurable logic Laboratories cmos logic circuits logic devices Immune system Magnetic field measurement Integrated circuit interconnections Random access memory Power supplies

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Designing robust ultra-low power circuits

Designing robust ultra-low power circuits

引用

International Electron Devices Meeting (IEDM)

作者： Dennis Sylvester Scott Hanson Mingoo Seok Yu-Shiang Lin David Blaauw University of Michigan Ann Arbor USA

Ubiquitous sensing systems, with a single node or thousands of nodes, are quickly becoming a viable technology option with the advancement of circuit and sensor design. In such a system, the most basic building block is an inexpensive sensor node with data processing and storage, off-chip communication, sensing elements, and a power source all linked within a robust package ideally with a volume on the order of lmm'. The sensor node must have a lifetime on the order of months or years. Due to the limitations of power sources, the most pressing implication of this lifetime requirement is that the power consumption of all components must be minimized.

关键词： Robustness Energy consumption Low voltage Memory management Sensor systems cmos logic circuits Energy efficiency Technological innovation Energy management Batteries

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Design considerations for low-power high-performance mobile logic and memory interfaces

Design considerations for low-power high-performance mobile ...

引用

IEEE Asian Conference on Solid-State circuits (ASSCC)

作者： Robert Palmer John Poulton Andrew Fuller Judy Chen Jared Zerbe Rambus Inc. Chapel Hill NC USA Rambus Inc. Los Altos CA USA

This paper highlights design considerations for low-power, high-performance mobile memory and logic interfaces, based on the results from the 14 mW, 6.25 Gb/s transceiver test chip demonstrated in 90 nm cmos. One of the keys to achieving 2.25 mW/Gbps was the highly-sensitive, low-offset receiver. An accurate receiver enables low-swing signaling and requires less power and area from the transmitter. The smaller transceiver design in turn lowers the clock distribution power and improves the signal quality by presenting less loading to the clock and the channel, respectively. The improved signal quality enables even lower signal swing and a ldquospiral of goodnessrdquo continues. This paper examines these aspects in detail and discusses their potential implications to a broad spectrum of future low-power, high-performance mobile interface designs.

关键词： logic design Clocks Transmitters Transceivers Signal design Bandwidth Random access memory cmos logic circuits logic testing Prototypes

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Increasing minimum operating voltage (VDDmin) with number of cmos logic gates and experimental verification with up to 1Mega-stage ring oscillators

Increasing minimum operating voltage (VDDmin) with number of...

引用

International Symposium on Low Power Electronics and Design (ISLPED)

作者： Taro Niiyama Zhe Piao Koichi Ishida Masami Murakata Makoto Takamiya Takayasu Sakurai University of Tokyo Meguro-ku Tokyo Japan Semiconductor Technology Academic Research Center (STARC) Japan

In order to explore the feasibility of the large scale subthreshold logic circuits and to clarify the lower limit of supply voltage (V DD ) for logic circuits, the dependence of minimum operating voltage (V DDmin ) of cmos logic gates on the number of stages, gate types and gate width is systematically measured with 90-nm cmos ring oscillators (RO's). The measured average V DDmin of inverter RO's increased from 90 mV to 343 mV when the number of RO stages increased from 11 to 1 Mega, which indicates the difficulty of the V DD scaling in the large scale subthreshold logic circuits. The dependence of V DDmin on the number of stages is calculated with the subthreshold current model with random threshold voltage (V TH ) variations and compared with the measured results, which confirm the tendency of the measurement.

关键词： cmos logic circuits Voltage-controlled oscillators logic gates Ring oscillators logic circuits Large-scale systems Current measurement Inverters Subthreshold current Threshold voltage

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Particularities of cyclic intelligent ADC design, implementation and adjusting

Particularities of cyclic intelligent ADC design, implementa...

引用

International Conference on Signals and Electronic Systems, ICSES

作者： Anatoliy Platonov Jakub Jasnos Konrad Jedrzejewski Lukasz Malkiewicz Zbigniew Jaworski Elzbieta Piwowarska Pawel Studzinski Warsaw University of Technology Institute of Electronic Systems Warsaw Poland Institute of Micro and Optoelectronics Warsaw Poland Tele & Radio Research Institute Warsaw Poland

The paper presents the results of design, implementation and adjusting of the cmos version of the hardware prototype of new ldquointelligentrdquo cyclic analog-to-digit converter (IC ADC). There are presented the concept of intelligent conversion, main principles of practical implementation, main stages and particularities of design and adjusting the IC ADC.

关键词： Signal design Paper technology Hardware cmos integrated circuits Analog integrated circuits Digital integrated circuits Analog computers cmos logic circuits Read only memory Prototypes

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A Mature Methodology for Implementing Multi-Valued logic in Silicon

A Mature Methodology for Implementing Multi-Valued Logic in ...

引用

International Symposium on Multiple-Valued logic

作者： Mark H. Nodine Craig M. Files Intrinsity Inc. Austin TX USA

This paper gives an overview of methods proposed for implementing multi-valued logic in cmos and then describes Intrinsity's patented Fast 14 reg Technology as a mature methodology for silicon implementation of multi-valued logic. To the authors' knowledge, no previous method of implementing multi-valued logic has been demonstrated with a design of the complexity of a microprocessor core. Fast 14 Technology is based upon three fundamental characteristics including the use of (1) footed NMOS transistor domino logic, (2) multi-phased overlapping clocks, and (3) 1-of-N encoding of MVL signals. To provide additional opportunities for power optimization, the concepts of null value and mutex properties are introduced, presenting additional challenges for MVL representation and synthesis.

关键词： Multivalued logic Silicon cmos technology MOSFETs cmos logic circuits Voltage Circuit simulation Microprocessors Clocks Encoding

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High performance current-mode differential logic

High performance current-mode differential logic

引用

Asia and South Pacific Design Automation Conference

作者： Ling Zhang Jianhua Liu Haikun Zhu Chung-Kuan Cheng Masanori Hashimoto Department Computer Science & Engineering University of California San Diego CA USA Altera Corporation San Jose CA USA Qualcomm Inc. San Diego CA USA Department Information Systems Engineering Osaka University Osaka Japan

ISBN: (纸本)9781424419210

This paper presents a new logic style, named Current-Mode Differential logic (CMDL), that achieves both high operating speed and low power consumption. Inspired by the low-voltage swing (LVS) logic, CMDL uses a shunt resistor at the differential output to obtain constant low swing signal without the need to reset low. Furthermore, conditional shunt transistors are used for the internal nodes to prevent high-voltage swing, thus entirely eliminate the power-hungry clocked reset network in LVS circuits. We show that the CMDL is suitable for high-end microprocessor integer core by providing three datapath modules implemented in CMDL. Our simulation results indicate that, operating at comparable speed with LVS logic, CMDL circuits can achieve up to 50% reduction of delay-power product compared to cmos logic and LVS logic. In addition, CMDL reduces the power consumption of LVS by up to 40%.

关键词： Clocks cmos logic circuits Energy consumption Delay Resistors Voltage Microprocessors Frequency Switches logic circuits

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A 10-bit 300MHz 0.1mm2 triple-channel current-steering DAC 75.98dB SFDR in 65nm

A 10-bit 300MHz 0.1mm2 triple-channel current-steering DAC 7...

引用

International Symposium on VLSI Design, Automation and Test

作者： G.M. Hong Shih-Hsuan Hsu Yan-Hua Peng Alvin Hsin-Hung Chen Yi-Ti Wang Hsin-Hung Lu Infrastructure Research Development Center Faraday Technology Corporation Hsinchu Taiwan

For this paper, we used the UMC 65 nm 1P10M cmos logic process to design a 10-bit triple-channel current- steering DAC, which includes three channels of RGB. The analog/digital circuit was 2.5 V/1.2 V, the active area was 0.1 mm 2 per channel, and INL/DNL were each less than plusmn 0.4/plusmn 0.23LSB. We obtained an SFDR exceeding 75.98 dB while consuming only 6.24 mW of power per channel.

关键词： Voltage cmos logic circuits Digital circuits Clocks Sampling methods Binary codes Virtual colonoscopy cmos process logic design Photonic band gap

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A full current-mode sense amplifier for low-power SRAM applications

A full current-mode sense amplifier for low-power SRAM appli...

引用

IEEE Asia-Pacific Conference on circuits and Systems

作者： Anh-Tuan Do Jeremy Low Yung Shern Zhi-Hui Kong Kiat-Seng Yeo Joshua Low Yung Lih Division of Circuits and System (EEE2) School of Electrical and Electronics Engineering Nanyang Technological University Singapore

A full current-mode sense amplifier is presented. It extensively utilizes the cross-coupled inverters for both local and global sensing stages, hence achieving ultra low-power and ultra high-speed properties simultaneously. Its sensing delay and power consumption are almost independent of the bit- and data-line capacitances. Extensive pre-layout simulation results based on a 1.8 V/0.18 mum cmos technology from Chartered Semiconductor Manufacturing Ltd. (CHRT) have verified that the new SA outperforms the best published designs with 64% and 45% speed and power consumption improvements respectively. Furthermore, the new design can operate down to a supply voltage of 1 V. These attributes of the proposed SA make it judiciously appropriate for the use in the contemporary high-complexity systems, which continually crave for low-power and high-speed characteristics.

关键词： Random access memory Energy consumption Inverters Delay High power amplifiers cmos logic circuits Voltage Capacitance cmos technology Central Processing Unit

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