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检索条件"主题词=CMOS Logic Circuits"

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PrSoC: Programmable System-on-chip (SoC) for silicon prototyping

PrSoC: Programmable System-on-chip (SoC) for silicon prototy...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Chun-Ming Huang Chien-Ming Wu Chih-Chyau Yang Chin-Long Wey National Chip Implementation Center Hsinchu Taiwan Department of Electrical Engineering National Central University Jhongli Taiwan

This paper presents a Programmable SoC (System- on-chip) design methodology which integrates multiple heterogeneous SoC design projects into a single chip such that the total silicon prototyping cost for these projects can be greatly reduced by sharing the common SoC platform. Results show that an integrated SoC platform is comprised of eight SoC projects. When these eight SoC projects are designed separately, the total area is approximately 143.03mm , while the area of the integrated platform is about 24.43mm . The area reduction is significant, so is the fabrication cost. Once the integrated platform chip is fabricated, three programming schemes are carried out to allow the integrated chip to act as the individual SoC design projects. A test chip is designed and implemented using the TSMC 0.13um cmos generic logic process technology.

关键词： System-on-a-chip Silicon Prototypes Costs logic testing Design methodology Fabrication cmos process cmos logic circuits logic design

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An 8B/10B encoder with a modified coding table

An 8B/10B encoder with a modified coding table

引用

IEEE Asia-Pacific Conference on circuits and Systems

作者： Yong-woo Kim Jin-ku Kang School of Electronic and Electrical Engineering Inha University Incheon South Korea

This paper presents a design of 8B/10B encoder with a modified coding table. The proposed encoder has been designed based on a reduced coding table with a modified disparity control block. After being synthesized using cmos 0.18 mum process, the proposed encoder shows the operating frequency of 343 MHz and occupies the chip area of 1886 mum 2 with 189 logic gates. It consumes 2.74 mW power. Compared to conventional approaches, the operating frequency is improved by 25.6% and chip area is decreased to 43%.

关键词： Encoding Decoding Switches cmos logic circuits cmos process Frequency synthesizers logic gates Clocks Data communication Optical fiber communication

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logical effort model extension with temperature and voltage variations

logical effort model extension with temperature and voltage ...

引用

International Workshop on Thermal Investigation of ICs and Systems (THERMINIC)

作者： Chun-Hui Wu Shun-Hua Lin Herming Chiueh System-on-Chip Design Laboratory Department of Communications EngineeringNational Nano Device Laboratories National Chiao Tung University Hsinchu Taiwan

The method of ldquological Effort Delay Modelrdquo allows designers to quickly estimate delay time and optimize logic paths. But the previous variances of logical effort models do not mention how to handle process, voltage, and temperature (PVT) variations appropriately, which may induce a serious misestimate. According to simulation results, delay time increases 21% while temperature increasing from 0degC to 125degC, and increases 2X while supply voltage decreasing from 1 V to 0.5 V in 90nm process. Thus a simple linear extended logical effort g, 1/g=(m t t+b t )V DD +C, supporting for temperature t and supply voltage VDD variations is presented. The proposed model enables designers to estimate the logic path delay and to optimize an N-stage logic network under different temperature and supply voltage conditions. After validation, the accuracy of this new extended logical effort model can achieve about 90%.

关键词： Temperature Voltage Delay estimation Delay effects Design optimization logic design Semiconductor device modeling Parasitic capacitance cmos logic circuits logic gates

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A nanoelectronic memory array design with improved performance

A nanoelectronic memory array design with improved performan...

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Canadian Conference on Electrical and Computer Engineering (CCECE)

作者： Mrinmoy Barua Z. Abid Department of Electrical and Computer Engineering University of Western Ontario London Canada

We present the design of a nanoelectronic memory array compatible with molecular switch (nanodevice) electrical characteristics. The proposed transmission gate based CMOL (hybrid cmos / molecular) memory cell surmounts the operational difficulties facing the existing CMOL cell. The control circuitry with improved multiplexer design is introduced in this paper. HSPICE simulation shows that the required voltage levels can be achieved by using the proposed designs. Yield improvement through replacing the defective cell with a free cell can be achieved using a proposed algorithm. Moreover, the proposed memory cell has the same area as the existing CMOL inverter cells allowing easier implementation of both logic and memory circuits on the same chip.

关键词： cmos technology Switches Nanoscale devices Voltage logic circuits Circuit simulation cmos logic circuits logic devices Pulse inverters Silicon

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An 8-bit 1.8 V 500 MS/s cmos DAC with a novel four-stage current steering architecture

An 8-bit 1.8 V 500 MS/s CMOS DAC with a novel four-stage cur...

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Santanu Sarkar Ravi sankar Prasad Sanjoy Kumar Dey Vinay Belde Swapna Banerjee Department of Electronics and Electrical Engineering Indian Institute of Technology Kharagpur India Texas Instruments Inc. Bangalore India Freescale Semiconductor India Private Limited Noida India

This paper presents an 8 bit 1.8 V 500 MSPS digital- to analog converter using 0.18mum double poly five metal cmos technology for frequency domain applications. The proposed DAC is composed of four unit cell matrix. A novel decoding logic is used to remove the inter block code transition (IBT) glitch. The proposed DAC shows less number of switching for a monotonic input and the product of number of switching and the current value associated with switching is also less than the segmented DAC. The SPICE simulated DNL and INL is 0.1373 LSB and 0.331 LSB respectively and are better than the segmented DAC. The proposed DAC also shows better SNDR and THD than the segmented DAC. The MATLAB simulated THD, SFDR and SNDR is more than 45 dB, 35 dB and 44 dB respectively at 500MS/s with a 10 MHz input sine wave with incoherent timing response between current switches.

关键词： cmos technology Analog-digital conversion Digital-to-frequency converters Frequency domain analysis Matrix converters Decoding cmos logic circuits Block codes SPICE MATLAB

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Differential ECL/CML Synthesis for SiGe Bicmos

Differential ECL/CML Synthesis for SiGe BiCMOS

引用

IEEE Symposium on Compound Semiconductor Integrated Circuit (CSICS)

作者： Hans Gustat Ulrich Jagdhold Frank Winkler Markus Appel Gerald Kell Department of Circuit Design IHP Microelectronics GmbH Frankfurt Germany Department of Computer Science Humboldt-Universität zu Berlin Berlin Germany Department of Informatics and Media Fachhochschule Brandenburg Brandenburg Germany

A novel SiGe ECL/CML design flow is presented for the first time. It provides cmos-style synthesis with differential SiGe Bicmos ECL standard cells. A first version works in a 95 GHz one-mask HBT technology up to abou... 详细信息

关键词： Silicon germanium Germanium silicon alloys Bicmos integrated circuits cmos technology Clocks Circuit synthesis cmos logic circuits logic design Libraries Heterojunction bipolar transistors

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Preparing Rearchitected Designs for Sequential Equivalence Checking

Preparing Rearchitected Designs for Sequential Equivalence C...

引用

International Workshop on Microprocessor Test and Verification (MTV)

作者： Mark Nodine Intrinsity Inc. Austin TX USA

This paper describes a tool called rapport which prepares rearchitected designs for sequential equivalence checking. This tool is applicable when an existing "golden" design is optimized for higher performance. Without such a tool, the optimizations would need to remain within a single module boundary, since equivalence checking tools require a one-to-one mapping between ports when proving two designs are equivalent. The tool is also able to handle arbitrary encodings of reference signals to produce design signals and retiming of signals.

关键词： Circuit testing Circuit simulation Encoding MOSFETs cmos logic circuits Design optimization Clocks Signal design Circuit synthesis Microprocessors

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Low-cost realization of toffoli gate for the low-cost synthesis of quantum ternary logic functions

Low-cost realization of toffoli gate for the low-cost synthe...

引用

International Conference on Computer and Information Technology (ICCIT)

作者： Md. Mehedi Hasan Department of Electrical and Electronic Engineering Bangladesh University of Engineering and Technology Dhaka Bangladesh

Reversible quantum computer system is one of the best choices for future computer systems. Multiple-valued logic especially ternary logic is a good candidate for the realization of reversible quantum computer. An efficient logic synthesis mechanism is essential for the low-cost realization. Toffoli gate is an important gate for quantum logic synthesis. It is the basic element for the Galois Field Sum of Product (GFSOP) expression based logic synthesis mechanism. So, for low-cost realization of any ternary logic function, a low-cost implementation of Toffoli gate is very necessary. This paper shows a low-cost, practically realizable, and efficient realization of 3-qutrit ternary Toffoli gate by using ion-trap realizable Muthukrishnan-Stroud gate. This realization is more efficient and less costly than other realizations.

关键词： Multivalued logic Quantum computing logic functions Costs Circuit synthesis cmos logic circuits logic circuits Network synthesis Information technology DH-HEMTs

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Evaluation of power supply noise in cmos and low noise logic cells

Evaluation of power supply noise in CMOS and low noise logic...

引用

International Zurich Symposium on Electromagnetic Compatibility (EMC Zurich)

作者： Junfeng Zhou Wim Dehaene ESAT MICAS Katholieke Universiteit Leuven Heverlee Belgium

In digital designs, it becomes more and more important to reduce the supply current variations (di/dt noise) they induce in the supply lines. This is due to the fact that steep variations in supply current give rise to EM (Electro-Magnetic) radiation. In this paper, two new modified low-noise logic styles - Complementary-CBL (C-CBL) and Enhanced-CSL (E-CSL) are presented in which the di/dt noise due to the switching is reduced greatly with respect to standard cmos (Scmos) circuits. Furthermore, a comparison with existing alternative low noise techniques shows that, for the same supply voltage and the same power consumption, the Enhanced-CSL circuits have smaller area, higher noise margins and smaller propagation delay.

关键词： Power supplies cmos logic circuits Circuit noise Current supplies Noise reduction Electromagnetic radiation Switching circuits Voltage Energy consumption Propagation delay

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Low-voltage limitations and challenges of nano-scale cmos LSIs - A personal view of memory designer -

Low-voltage limitations and challenges of nano-scale CMOS LS...

引用

IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Kiyoo Itoh Central Research and Development Laboratory Hitachi Limited Kokubunji Tokyo Japan

The minimum operating voltage (V min ) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V min that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V T ) of MOSFETs. The V min , however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce V T variations.

关键词： Random access memory Read-write memory Voltage logic circuits cmos logic circuits MOSFETs Degradation Subthreshold current Flip-flops logic arrays

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