检索结果-内蒙古大学图书馆

A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realized by Dielectric-fuse RRAM Devices Featuring Ultra-High Reliable Retention and Good Endurance for Embedded Applications

A Novel ReWritable One-Time-Programming OTP (RW-OTP) Realize...

引用

International Symposium on VLSI Technology, Systems and Application (VLSI-TSA)

作者： Cheng, H. W. Hsieh, E. R. Huang, Z. H. Chuang, C. H. Chen, C. H. Li, F. L. Lo, Y. M. Liu, C. H. Chung, Steve S. Natl Chiao Tung Univ Dept Elect Engn Hsinchu 30050 Taiwan Natl Chiao Tung Univ Inst Elect Hsinchu 30050 Taiwan Natl Taiwan Normal Univ Dept Mechatron Engn Taipei Taiwan

ISBN: (纸本)9781538648254

A novel concept of OTP has been demonstrated to create another feasibility to allow re-writable capability before storing the data. This OTP is named ReWritable One-time programming (RW-OTP) memory. With RW-OTP, users can do the test by modifying the contexts repeatedly before finalizing the stored data. To implement the memory cell, it consists of a gate-floated FinFET and an RRAM where a bilayer has been designed as a thicker dielectric layer with resistive-switching property on a thinner dielectric-fuse layer. Moreover, the process of RW-OTP is fully compatible with the state-of-the-art cmos logic technology. The result shows that the memory cell exhibits high retention and good endurance. With proper use of RW-OTP, the users can not only reduce error jobs cost-efficiently but also can develop various applications for their needs. This memory cell is very promising for embedded applications.

关键词： cmos logic circuits MOSFET resistive RAM

来源：评论

学校读者我要写书评

暂无评论

A High-Speed Energy-Efficient cmos Dynamic Latch Comparator for Low-Voltage Applications

A High-Speed Energy-Efficient CMOS Dynamic Latch Comparator ...

引用

IEEE UP Section Conference on Electrical Computer and Electronics (UPCON)

作者： Vikrant Varshney Ankur Kumar Avaneesh Kumar Dubey Priyanka Singh R. K. Nagaria Motilal Nehru National Institute of Technology Allahabad Prayagraj U.P. India

ISBN: (纸本)9781728134567

This paper presents an energy-efficient low-voltage double-tail dynamic latch comparator which shows high switching speed in comparison to conventional design. The proposed comparator is designed using improved pre-amplifier stage in which hybrid design style is adopted to enhance latch speed with optimum power. As a result, energy efficiency is improved. The analytical expressions for delay calculation are also derived for the proposed comparator. The rigorous simulations are analyzed in CADENCE SPECTRE at 90nm cmos technology with 1V power supply. The mismatch analysis for offset voltage is validated using Monte-Carlo simulations at 200 samples. The simulations and analytical derivations corroborate that the enhanced speed is achieved with low-offset and optimized power dissipation. The simulation results confirm that the proposed design is about 2 times faster, 52.89% more energy efficient, and minimizes 27.51% offset voltage in contrast of conventional dynamic comparator at the cost of 20.39μW power consumption and 54.03μm 2 active die area.

关键词： cmos logic circuits comparators (circuits) energy conservation flip-flops low-power electronics Monte Carlo methods preamplifiers preamplifiers Monte Carlo technique cmos logic circuits low-power electronics flip-flops Energy conservation COMPARATORS offset voltage Low voltage Energy efficiency Latch Device Component

来源：评论

学校读者我要写书评

暂无评论

Efficient Implementation of the Data Link Layer at the Receiver of JESD204B

Efficient Implementation of the Data Link Layer at the Recei...

引用

International Conference on Intelligent Computing, Automation and Systems (ICICAS)

作者： Xue Li Ying Liu Wuhan Polytechnic Wuhan China

ISBN: (数字)9781728161068

ISBN: (纸本)9781728161075

JESD204B is the latest industry standard for the interface between data converters and logic devices. A quad-byte parallel implementation of the data link layer in JESD204B receiver was proposed, a series of data processing, the synchronization control and peripheral auxiliary functions prescribed in JESD204B protocol were implemented. Use of a topological structure for parallel processing control information and data information accelerated the circuit speed and reduced the number of logic layers of synchronization control module; furthermore the theoretical circuit operating clock frequency was reduced from 1.25 GHz to 312.5 MHz which made it easier to be implemented in low-cost cmos technology. A docking verification between the Verilog model and XLINX's official JESD204B 6.1v receiver IP core was performed, and the simulation results were consistent with the theoretical analysis results; in addition, the design was synthesized with SMIC 180nm cmos technology at Design Compiler platform, and the synthesis results show that the design fully met the JESD204B protocol specification in operating frequency, cell area and power consumption.

关键词： clocks cmos logic circuits logic design parallel processing receivers synchronisation Receivers cmos logic circuits logic design PARALLEL PROCESSING (COMPUTERS) Timing devices Synchronous control data link layer data converters clock frequency topological structure

来源：评论

学校读者我要写书评

暂无评论

Design of Power Efficient Vedic Multiplier using Adiabatic logic

Design of Power Efficient Vedic Multiplier using Adiabatic L...

引用

IEEE UP Section Conference on Electrical Computer and Electronics (UPCON)

作者： Kuheli Dutta Sudipta Chattopadhyay Vaishna Biswas Suman Roy Ghatak Netaji Subhash Engineering College Kolkata India Jadavpur University Kolkata India

ISBN: (纸本)9781728134567

Various “arithmetic operations”, “signal and image processing systems” and “communication devices” incorporate multipliers as the basic element. Vedic mathematics is an ancient mathematical system which focuses on solving tedious problems using 16 Vedic Sutras in a simpler and faster manner. The evolution of technology demands for “low power design” in the domain of integrated circuit. This led to the invention of varied adiabatic logic for low power operations. The uniqueness of Vedic mathematics and adiabatic logic is combined to design high speed and power-efficient multipliers. In this paper, a new adiabatic logic “Complementary Pass Transistor Adiabatic logic” (CPAL) is used to design 8-bit Vedic multiplier. To authenticate the superiority of the proposed design, comparative performance analysis is carried out with respect to cmos and other adiabatic logics like 2N-2N2P and “Efficient Charge Recovery logic” (ECRL) based on 150nm technology. The simulation has been accomplished by the use of TANNER SPICE 16 tool. Simulation result validates the reduction of Power Delay Product (PDP) of the proposed CPAL Vedic multiplier design in comparison to the aforementioned techniques. The proposed technology offers a power-efficient solution for modern designs.

关键词： cmos logic circuits digital arithmetic logic design low-power electronics multiplying circuits SPICE Multiplying circuits Digital arithmetic cmos logic circuits logic design low-power electronics SPICE Formal logic Adiabatic Image processing systems

来源：评论

学校读者我要写书评

暂无评论

A variation and noise tolerant wide fan-in OR-logic Domino circuit

A variation and noise tolerant wide fan-in OR-Logic Domino c...

引用

IEEE UP Section Conference on Electrical Computer and Electronics (UPCON)

作者： Ankur Kumar Vikrant Varshney Priyanka Singh R. K. Nagaria Motilal Nehru National Institute of Technology Allahabad Allahabad U.P. India

ISBN: (纸本)9781728134567

This paper presents a new wide fan-in domino OR-gate which reduces variability and power dissipation simultaneously at enhanced noise margin. In this work, some crucial modifications in keeper and evaluation network are done to decrease the process variability and leakage current. Primarily, two extra PMOS transistors are stacked at the top of keeper transistor in source degeneration style to reduce the transconductance which reduce the variability. Second, an effective arrangement is added to control the switching activity of keeper transistor which reduce dynamic power consumption and leakage current of the proposed domino. Further, noise immunity is improved because of efficient charging and discharging of dynamic node. The simulations are done under cadence virtuoso environment for wide fan-in (8, 16, 32 and 64-input) OR-gates using 45nm cmos technology node at 1V power supply and 1GHz clock frequency respectively. The simulation results indicate 46% and 48% reduction in delay and power variability, respectively along with 50% improvement in noise margin of proposed work as compared to conventional domino gate.

关键词： cmos logic circuits integrated circuit noise leakage currents logic design logic gates low-power electronics MOSFET power consumption metal-oxide-semiconductor field effect transistors cmos logic circuits Integrated circuit noise Power consumption low-power electronics logic design logic gates Noise margins fan-in leakage currents Leakage currents

来源：评论

学校读者我要写书评

暂无评论

Performance Comparison of Explicit Pulsed Flip-Flops in Low Power and High-Speed Applications

Performance Comparison of Explicit Pulsed Flip-Flops in Low ...

引用

2018 International Conference on circuits and Systems in Digital Enterprise Technology, ICCSDET 2018

作者： John, Kuruvilla Vinod Kumar, R.S. Kumar, S.S. ECE Department Noorul Islam Centre for Higher Education Thucklay India EIE Department Noorul Islam Centre for Higher Education Thucklay India

ISBN: (纸本)9781538605769

This paper presents a comparative study in the performance of three pulse flip-flops (P-FFs) designs with an explicit pulse generation structure. It includes explicit pulse triggered data close to output flip-flop (ep-DCOFF), the conditional discharging flip-flop (CDFF) and signal feed-through flip-flop (SFTFF). The Conditional discharging technique is incorporated in CDFF. This flip-flop is having the advantages of reduced internal switching activities, fewer glitches at the output, negative setup time and small input-to-output delay features. The SFTFF is having a signal feed-through mechanism due to its true single phase clock latch based structure. The SFTFF reduces the problem of longest discharge path exists in other conservative flip-flops with the explicit style of pulse production. This design features a better performance in speed and power. The performance of P-FF compared using cadence software in cmos 90nm technology. The post-layout simulation result shows that SFTFF outperforms ep-DCOFF and CDFF by 36.8% and 23.4% in power consumption respectively. The SFTFF is having the advantage of 22.4% and 48.2% in Data-to-Q delay when compared with ep-DCOFF and CDFF respectively. © 2018 IEEE.

关键词： cmos logic circuits flip-flops logic design low-power electronics flip-flops cmos logic circuits logic design low-power electronics Explicit discharge path Pulses LOW POWER feed-through

来源：评论

学校读者我要写书评

暂无评论

An 80-mV-to-1.8-V Conversion-Range Low-Energy Level Shifter for Extremely Low-Voltage VLSIs

引用

IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2017年第8期64卷 2026-2035页

作者： Matsuzuka, Ryo Hirose, Tetsuya Shizuku, Yuzuru Shinonaga, Kyohei Kuroki, Nobutaka Numa, Masahiro Kobe Univ Grad Sch Elect & Elect Engn Kobe Hyogo 6578501 Japan Panasonic Corp Kadoma Osaka 5708501 Japan Ricoh Elect Devices Corp Osaka 5638501 Japan

We present a low-power and low-energy level shifter (LS) circuit that can convert extremely low-voltage input into high-voltage output. The proposed LS consists of a pre-amplifier (pre-AMP) and an output latch. The pre-AMP employs a logic error correction circuit, which generates an operating current for the pre-AMP only when the logic levels of the input and output do not correspond. The pre-AMP generates complementary amplified signals, and the latch converts them into full-swing outputs. Measurement results demonstrated that the proposed LS fabricated in 0.18-mu m cmos technology was able to convert an extremely low-voltage input of 80 mV into a high-voltage output of 1.8 V. The energy of the proposed LS was 0.35 pJ, when the low supply voltage, high supply voltage, and input pulse frequency were 0.4 V, 1.8 V, and 10 kHz, respectively. The static power dissipation without input was 0.12 nW.

关键词： cmos logic circuits low-power electronics multiple supply voltages level shifters low-voltage circuits

来源：评论

学校读者我要写书评

暂无评论

Interconnect Performance and Energy-Per-Bit for Post-cmos logic circuits: Modeling, Analysis, and Comparison with cmos logic

Interconnect Performance and Energy-Per-Bit for Post-CMOS Lo...

引用

Joint Conference on IEEE International Interconnect Technology Conference / 20th European Workshop on Materials for Advanced Metallization (IITC/MAM)

作者： Rakheja, Shaloo Naeemi, Azad Georgia Inst Technol Sch Elect & Comp Engn Atlanta GA 30332 USA

ISBN: (纸本)9781457705021

To overcome the energy dissipation limit facing virtually all field-effect devices including cmos switches, there is a global search for devices using alternate state variables as the token of information. In this paper, physical models for latency and energy dissipation associated with various transport mechanisms are reviewed. Using stochastic wire length distribution models based on Rent's rule, the dependence of the average interconnect delay and energy dissipation on the number of gates in a circuit is obtained for alternative post-cmos logic circuits. Further, it is demonstrated that the required number of repeaters increases rapidly with the circuit size if the token of information decays as it propagates (e.g. spin relaxation for electron spin). This puts an upper bound on the circuit size. For a spin relaxation length of L-s=2 mu m, the maximum circuit size for random logic is limited to 40 gates if less than 10% of the switches are to be used as interconnect repeaters and if the signal amplitude at the driver is twice the receiver's threshold. This maximum circuit size increases to 2000 gates if the spin relaxation length is increased to 8 mu m at the same signal amplitude.

关键词： cmos integrated circuits cmos logic circuits cmos switches Delay Energy dissipation Integrated circuit interconnections logic gates Receivers Rent rule Repeaters alternate state variables energy dissipation energy-per-bit field-effect devices integrated c

来源：评论

学校读者我要写书评

暂无评论

Design of non-restoring divider in quantum-dot cellular automata technology

引用

IET circuits DEVICES & SYSTEMS 2017年第2期11卷 135-141页

作者： Mohammadi, Mohammad Gorgin, Saeid Mohammadi, Majid Islamic Azad Univ Dezful Branch Dept Comp Dezful Iran Iranian Res Org Sci & Technol Dept Elect & Informat Technol Tehran Iran Shahid Bahonar Univ Kerman Dept Comp Engn Kerman Iran

Among all basic arithmetic operations, the division is the most complex one. On the other hand, working on post-complementary metal-oxide-semiconductor (cmos) technology attracts attention of many researchers, while the progress of miniaturisation in cmos technology faced physical limits. Therefore, in this study, the authors propose a non-restoring divider in quantum-dot cellular automata (QCA), as one of the most promising technology. To achieve an efficient divider, they propose a novel 1 bit full-adder and take advantage of improved design of XOR gate. This design has considerable improvements in terms of cell numbers, delay and area, compared with other dividers. The suggested design is simulated in QCADesigner software and acceptable results are achieved.

关键词： adders quantum-dot cellular automata technology word length 1 bit nonrestoring divider cellular automata full-adder logic gates dividing circuits cmos technology cell number XOR gate QCADesigner software quantum dots QCA technology complementary metal–oxide–semiconductor technology cmos logic circuits

来源：评论

学校读者我要写书评

暂无评论

The Impact of RTN on Performance Fluctuation in cmos logic circuits

The Impact of RTN on Performance Fluctuation in CMOS Logic C...

引用

49th Annual IEEE International Reliability Physics Symposium (IRPS)

作者： Ito, Kyosuke Matsumoto, Takashi Nishizawa, Shinichi Sunagawa, Hiroki Kobayashi, Kazutoshi Onodera, Hidetoshi Kyoto Univ Kyoto 6068501 Japan Kyoto Inst Technol Kyoto 6068585 Japan JST CREST Tokyo Japan

ISBN: (纸本)9781424491117

In this paper, the impact of Random Telegraph Noise (RTN) on cmos logic circuits observed in a Circuit Matrix Array is reported. We discuss the behavior of RTN under circuit operation, and reveal that the impact of RTN, which is much smaller than that of within-die variation in a 65nm process, can have a severe effect on the performance of a sequential logic gate under low voltage operation.

关键词： cmos logic circuits cmos logic circuits Delay Frequency conversion Low voltage Noise Oscillators Time frequency analysis circuit matrix array logic gates low voltage operation performance fluctuation random telegraph noise sequential circuits sequential logic gate size 65 nm

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：