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检索条件"主题词=CMOS Logic Circuits"

共 4677 条记录，以下是701-710 订阅

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Low-Voltage Scaling Limitations for Nano-Scale cmos LSIs

Low-Voltage Scaling Limitations for Nano-Scale CMOS LSIs

引用

2008 9th International Conference on Ultimate Integration on Silicon (ULIS 2008)

作者： Kiyoo Itoh Central Research Laboratory Hitachi and Limited Kokubunji Tokyo Japan

The minimum operating voltage (V{sub}(min)) of nano-scale LSIs is investigated, focusing on logic gates, SRAM cells, and DRAM sense amplifiers in LSIs. The V{sub}(min) that is governed by SRAM cells rapidly increases as devices are miniaturized due to the ever-larger variation of the threshold voltage (V{sub}T) of MOSFETs. The V{sub}(min), however, is reduced to the sub-one-volt region by using repair techniques and new MOSFETs (e.g., FD-SOIs and/or high-k metal gates) that can reduce V{sub}T variations.

关键词： Random access memory MOSFETs cmos logic circuits logic circuits logic gates Read-write memory logic arrays logic devices Threshold voltage Degradation

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C-Flash: An Ultra-Low Power Single Poly logic NVM

C-Flash: An Ultra-Low Power Single Poly Logic NVM

引用

IEEE International Memory Workshop (IMW)

作者： Y. Roizin E. Aloni A. Birman V. Dayan A. Fenigstein D. Nahmad E. Pikhay D. Zfira Tower Semiconductor Limited Migdal Haemek Israel

ISBN: (纸本)9781424415465;1424415462

An ultra-low power logic NVM has currents <10 nA/cell in all operating regimes, high programming/erase speeds, excellent endurance/retention and allows strong Vdd fluctuations. The memory uses cmos inverter read-out principle (C-Flash) and F-N injection for programming and erase with voltages below +5 V. The memory is intended for RFID and advanced mobile applications requiring small/middle sized embedded memory modules.

关键词： Inverters Voltage Capacitors Testing logic programming Nonvolatile memory Virtual manufacturing cmos logic circuits Leakage current Prototypes

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A new dynamic differential logic style as a countermeasure to power analysis attacks

A new dynamic differential logic style as a countermeasure t...

引用

IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： L. Giancane P. Marietti M. Olivieri G. Scotti A. Trifiletti Dipartimento di Ingegneria Elettronica Università di Roma La Sapienza Rome Italy

Power analysis attacks exploit the existence of ldquoside channelsrdquo in implementations of cryptographic algorithms to extract secret data. The scientific literature reports consolidated methods - such as Differential Power Analysis (DPA) and Simple Power Analysis (SPA) - for extracting a secret cryptographic key through the sensing of the hardware power consumption. We propose a novel dynamic and differential cmos logic style as a countermeasure against power attacks on cryptographic devices. The proposed logic family exploits the idea of using signals with 3 possible states and operates with power consumption ideally independent on both the logic values and the sequence of data. We have designed a set of logic gates, flip flops and a simple S-BOX, and compared the S-BOX against previously published secure logic styles in terms of transistor count, power consumption and correlation between data and power dissipation.

关键词： cmos logic circuits logic devices Cryptography Energy consumption Data mining logic design Algorithm design and analysis Hardware logic gates Power dissipation

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Soft-Error Vulnerability of Sub-100-nm Flip-Flops

Soft-Error Vulnerability of Sub-100-nm Flip-Flops

引用

IEEE Symposium on On-Line Testing (IOLTS)

作者： Tino Heijmen NXP Semiconductors Netherlands

The soft-error vulnerability of flip-flops has become an important factor in IC reliability in sub-100-nm cmos technologies. In the present work the soft-error rate (SER) of a 65-nm flip-flop has been investigated with the use of alpha-accelerated testing. Simulations have been applied to study the flip-flop SER sensitivity in detail. Furthermore, an easy-to-use approach is presented to make an accurate estimation of the contribution of flip-flops to the SER of an IC. The method is applicable to frequencies well below 1 GHz. The approach is based on a set of expressions for the timing vulnerability factor (TVF) of the master and slave latches of the flip-flop. With this approach it is possible to make an accurate estimation of the flip-flop SER parameters.

关键词： Flip-flops cmos technology Frequency estimation cmos integrated circuits Master-slave cmos logic circuits Timing Latches cmos process Random access memory

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Analysis and Design of a 50-GHz 2:1 cmos CML Static Frequency Divider Based on LC-tank

Analysis and Design of a 50-GHz 2:1 CMOS CML Static Frequenc...

引用

European (Formerly European Gallium Arsenide and Other Semiconductors Application Symposium - EGASS) Microwave Integrated Circuit Conference (EuMIC)

作者： Yuan Mo Efstratios Skafidas Rob Evans Iven Mareels National ICT Australia Department of Electrical and Electronic Engineering University of Melbourne Parkville VIC Australia

In this paper, a 2:1 current model logic (CML) frequency divider operating at frequencies up to 50 GHz is reported. A novel circuit topology is employed, which consists of the conventional CML structure with LC-tank components as the output load of the divider. An analytical model of the proposed frequency divider is developed and a new method is presented to estimate the divider's performance. The proposed CML frequency divider contains four spiral inductors and is fabricated on standard 130-nm cmos technology. The division range of the proposed divider was measured from 30 GHz to 50 GHz with 11.7 mW power dissipation at a 1.5-V supply voltage.

关键词： Frequency conversion Frequency estimation cmos technology Semiconductor device modeling cmos logic circuits Circuit topology Analytical models Spirals Inductors Power measurement

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Modeling and Optimization of Switching Power Dissipation in Static cmos circuits

Modeling and Optimization of Switching Power Dissipation in ...

引用

IEEE Computer Society Annual Symposium on VLSI

作者： Adnan Kabbani Department of Electrical and Computer Engineering Ryerson University Toronto Canada

This paper introduces a simple and yet accurate closed-form expression to estimate the switching power dissipation of static cmos gates. The developed model depends on normalizing a gate- switching power to that of the unit standard inverter and it accounts for the effect of internodal capacitances. For different loads, gates and sizes, the developed model shows a good agreement with Spectre simulations using BSIM3v3 model and UMC 0.13 mum technology. The average error introduced by the model is about 2.7%. Moreover, the model has been used to optimize the switching power of a logical path under a specific required time constraint. For the considered scenarios, an average power saving of 20% and power-delay product of 23% are obtained compared to previous techniques.

关键词： Semiconductor device modeling Switching circuits Power dissipation Inverters Very large scale integration Capacitance cmos logic circuits Closed-form solution Time factors Design optimization

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Mechanism of via etch striation and its impact on contact resistance & breakdown voltage in 65nm cu low-k interconnects

Mechanism of via etch striation and its impact on contact re...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Wu Sun Man-Hua Shen Xin-Peng Wang Hai-Yang Zhang Xiao-Ming Yin Shih-Mou Chang Semiconductor Manufacturing International Corporation Beijing China

ISBN: (纸本)9781424421855

The mechanism of two kinds of via etch striation (type I and type II) has been investigated to improve contact resistance (Rc) uniformity and solve breakdown voltage (VBD) issue in 65 nm Cu low-k interconnects. Heavy etching polymer deposition on the sidewall of capping layer and rapid photo-resist (PR) consumption on PR shoulder are two main resources to result in via etch striation. The effects of both via etch striations on Rc and VBD can be decoupled. Type I striation related to barc open (BO) step leads to worse Rc uniformity while type II striation formed in main etch (ME) and over-etch (OE) step degrades VBD performance.

关键词： Contact resistance Polymers Dielectrics Dry etching Plasma applications Sun Semiconductor device manufacture Degradation Chemicals cmos logic circuits

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Built-In Current Monitor for IDDQ Testing in cmos 90 nm Technology

Built-In Current Monitor for IDDQ Testing in CMOS 90 nm Tech...

引用

IEEE Design and Diagnostics of Electronic circuits and Systems (DDECS)

作者： Marcin J. Beresinski Tomasz Borejko Witold A. Pleskacz Viera Stopjakova Warsaw University of Technology Institute of Microelectronics and Optoelectronics Warsaw Poland Twinteq Warsaw Poland Department of Microelectronics Slovak University of Technology Bratislava Slovakia

In this paper, a built-in current (BIC) monitor for testing low-voltage digital cmos circuits is presented. The monitor is designated for typical I DDQ testing as well as for characterization of supply current values for different test vectors. Voltage drop across the monitor during measurement and the switching phase are minimized. A wide range of currents is supported. Abilities and limitations of the BIC monitor were verified through simulations. Results of post layout simulations are presented as well. The design was implemented in UMC cmos 90 nm technology.

关键词： cmos technology Monitoring Circuit testing Threshold voltage Current supplies Microelectronics Circuit faults cmos logic circuits Circuit simulation logic testing

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Opportunities and Challenges in Multi-Times-Programmable Floating-Gate logic Non-Volatile Memories

Opportunities and Challenges in Multi-Times-Programmable Flo...

引用

IEEE International Memory Workshop (IMW)

作者： Bin Wang Yanjun Ma Impinj Inc. Seattle WA USA

ISBN: (纸本)9781424415465;1424415462

Low bit count floating gate (FG) logic NVM (LNVM) developed in baseline logic process is finding increasing use in system-on-chip (SOC) ICs due to its low cost and absence of extra process integration needs. This paper reviews the opportunities this technology brings to the eNVM fields and the technical challenges it faces. It also demonstrates that FG logic NVM is scalable to have 50A tunneling oxide to store the charge at 65 nm cmos technology node and beyond.

关键词： Nonvolatile memory cmos logic circuits Costs cmos technology Tunneling cmos process System-on-a-chip logic programming Process design Read-write memory

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Progress toward a single chip radio in cmos

Progress toward a single chip radio in CMOS

引用

Proceedings of the IEEE Dallas circuits and Systems Workshop (DCAS)

作者： Kenneth K. O. S. Yu C. Cao J.-J. Lin Y.-P. Ding Z.-B. Li M.-H. Hwang S.-H. Hwang L. Gao A. Sugavanam A. Verma X. Yang D. Shim E.-Y. Seok D. Arenas R. Bashirullah J. Lin R. Fox D. Tanner J. E. Brewer D. Taubenheim S. Machen P. Gorday F. Martin Department of Electrical and Computer Engineering University of Florida USA University of Florida USA Motorola Labs

• On-chip antenna pair gain at 24GHz is not optimal but sufficient for communication over 5 m near ground. 10-m range is possible if the antennas sit ∼ 50 cm above ground. • It should be possible to communicate to a UAV flying at 50–100m above the ground. • 24-GHz RF circuits with reasonable power consumption should be possible in 130-nm cmos. It needs to be drastically reduced for unattended sensor applications. • The crystal reference frequency stability requirement has been relaxed such that use of an LC oscillator is possible. • Dual conversion architecture should enable integration of a transmitting antenna, PA and VCO on the same silicon substrate. • Power consumption reduction is the last remaining challenge. Lower frequency operation.

关键词： Radio frequency Transmitting antennas Baseband cmos process Antenna accessories cmos logic circuits Receiving antennas Switches Phase locked loops Coupling circuits

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