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检索条件"主题词=CMOS Logic Circuits"

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Technologies and materials for memory with full compatibility to cmos

Technologies and materials for memory with full compatibilit...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Min-hwa Chi HanMing Wu SOC Technology Development Semiconductor Manufacturing International (Shanghai) Corp. Shanghai P.R.C.

As cmos scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full cmos compatibility, such as logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility in BEOL. Thus, fully cmos compatible SOC is a promising trend into the future.

关键词： cmos technology Random access memory Nonvolatile memory High-K gate dielectrics MIM capacitors cmos logic circuits High K dielectric materials Tunneling SONOS devices Channel hot electron injection

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Soft error reliability improvements for implantable medical devices

Soft error reliability improvements for implantable medical ...

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Annual International Symposium on Reliability Physics

作者： Mark Porter Jeff Wilkinson Kevin Walsh Brian Sierawski Kevin Warren Robert A. Reed Gyorgy Vizkelethy Medtronic Microelectronics Center Tempe AZ USA Medtronic Inc. MN USA Institute for Space and Defense Electronics Vanderbilt University Nashville TN USA Department of Electrical Engineering Vanderbilt University Nashville TN USA Sandia National Laboratories Albuquerque NM USA

As the expectations of physicians and patients have matured, the desire to utilize advanced cmos technologies to provide increasingly sophisticated therapeutic and diagnostic capabilities has grown. This has pushed the high reliability implantable device business into the use of processes that are much more susceptible to soft error events than in the past. This paper discusses experimental and modeling results of logic upsets in a 0.25 mum cmos IC process.

关键词： Implantable biomedical devices Flip-flops cmos technology Clocks Ion beams Laboratories Circuit testing Space technology Integrated circuit modeling cmos logic circuits

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A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Power 8-bit Folding/Interpolating ADC

A Subthreshold SCL Based Pipelined Encoder for Ultra-Low Pow...

引用

Norchip

作者： Mohammad Beikahmadi Armin Tajalli Yusuf Leblebici Microelectronic Systems Laboratory (LSM) Ecole Polytechnique Fédérale de Lausanne Switzerland

The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data converter using this technique. The encoder is designed and characterized in a conventional 0.18 ¿m cmos technology, and it is capable of operating over a wide frequency range (10 kHz-50 MHz) without the need of resizing the transistors or scaling the voltage levels. The speed and power consumption of the encoder are proportional to the bias currents of the gates. The supply voltage of the circuit can be as low as 350 mV.

关键词： Voltage MOS devices Switches logic circuits Energy consumption cmos logic circuits logic design Crosstalk cmos technology Frequency

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High speed and ultra low voltage cmos latch

High speed and ultra low voltage CMOS latch

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IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Y. Berg O. Mirmotahari S. Aunet Department of Informatics University of Oslo Oslo Norway

In this paper we present a novel ultra-low-voltage (ULV) cmos latch and a flip-flop. The gates offer increased speed compared to other cmos logic styles for ultra low supply voltages. The timing detail is discussed and an ULV latch is presented. ULV logic gates can be operated at a clock frequency more than 10 times than the maximum clock frequency of a similar complementary cmos gate assuming a very low supply voltage. The latch may be applied in a ULV flip-flop as well. The simulated data for the latch presented is obtained using the Spectre simulator provided by Cadence and valid for a 90nm cmos process.

关键词： Low voltage cmos logic circuits Latches cmos process Threshold voltage Clocks Frequency Flip-flops logic gates MOSFETs

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Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes

Non-contact Testing for SoC and RCP (SIPs) at Advanced Nodes

引用

IEEE International Test Conference

作者： B. Moore M. Mangrum C. Sellathamby M. Reja T. Weng B. Bai E. Reid I. Filanovsky S. Slupsky Scanimetrics Inc. Edmonton AB Canada Freescale Semiconductor Inc. TX USA Department of Electrical and Computer Engineering University of Alberta Edmonton AB Canada

Non-contact methods for testing system-on-chip (SoC) and system in package (SIP) assemblies are presented. This method allows for high speed testing at the wafer level for SoCs as well as testing during and after assembly for panel or wafer level SIP technologies. Wafer testing at advanced nodes is carried out without damaging underlying metallurgy - an issue with current contact testing techniques. The technology utilizes non-contact GHz short-range transceivers to transfer test signals and results to and from SoC ICs. The wireless probes convert standard tester ATE logic levels to high frequency RF (GHz) transceiver signals and thus allow the use of standard test equipment. A reduced set of contact probes are used for test power only. A 45 nm fully cmos compatible IC with wireless test transceivers is designed and fabricated. Enhancing the reliability and economics of IC manufacture by enabling non-contact testing of SoCs before and during packaging is a key benefit of this technology.

关键词： Transceivers Packaging Probes logic testing Integrated circuit testing System testing System-on-a-chip Wafer scale integration Assembly systems cmos logic circuits

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A low power 40nm cmos technology featuring extremely high density of logic (2100kGate/mm2) and SRAM (0.195μm2) for wide range of mobile applications with wireless system

A low power 40nm CMOS technology featuring extremely high de...

引用

International Electron Devices Meeting (IEDM)

作者： R. Watanabe A. Oishi T. Sanuki H. Kimijima K. Okamoto S. Fujita H. Fukui K. Yoshida H. Otani E. Morifuji K. Kojima M. Inohara H. Igrashi K. Honda H. Yoshimura T. Nakayama S. Miyake T. Hirai T. Iwamoto Y. Nakahara K. Kinoshita T. Morimoto S. Kobayashi S. Kyoh M. Ikeda K. Imai M. Iwai N. Nakamura F. Matsuoka System LSI Division Toshiba Corporation Japan Advanced Device Development Division NEC Electronics Corporation Limited Yokohama Japan Process and Manufacturing Engineering Center Toshiba Corporation Japan

Extremely high density cmos technology for 40 nm low power applications is demonstrated. More than 50% power reduction is achieved as a SoC chip by aggressive shrinkage and low voltage operation of RF devices. Gate density of 2100 kGate/mm 2 is realized by breaking down conventional trade-off of leakage power and performance with three key approaches. 0.195 mum 2 SRAM with excellent static noise margin is also accomplished by minimizing random impurity fluctuation using Hf doped silicate as gate dielectrics. In addition, novel DFM (Design for Manufacturing) techniques are introduced for systematic yield improvement.

关键词： cmos technology cmos logic circuits logic devices Low voltage Radio frequency Random access memory Impurities Fluctuations Hafnium Dielectrics

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Statistical leakage modeling in cmos logic gates considering process variations

Statistical leakage modeling in CMOS logic gates considering...

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IEEE International Conference on Integrated Circuit Design and Technology (ICICDT)

作者： Carmelo D'Agostino Philippe Flatresse Edith Beigne Marc Belleville STMicroelectronics Crolles FTM/DAIS MINATEC CEA-LETI Grenoble CEA-LETI Grenoble MINATEC

The dramatic increase in leakage current, coupled with the swell in process variability in nano-scaled cmos technologies, has become a major issue for future IC design. Moreover, due to the spread of leakage power values, leakage variability cannot be neglected anymore. In this work an accurate analytic estimation and modeling methodology has been developed for logic gates leakage under statistical process variations. The developed methodology is completely based on BSIM4 equations, implemented in Verilog-A, and applicable to any different cmos technologies (90 nm, 65 nm, etc), electrical simulators and models. For the first time subthreshold, gate, BTBT, and GIDL leakage variations are considered. Comparisons to Monte-Carlo simulation on 90 and 65 nm STMicroelectronics cmos technologies fully validate the accuracy of the proposed method and demonstrate the efficiency of the proposed analysis method.

关键词： cmos logic circuits Semiconductor device modeling cmos process logic gates cmos technology Leakage current cmos integrated circuits Gate leakage Differential equations Hardware design languages

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Speeding-up wide-fan in domino logic using a controlled strong PMOS keeper

Speeding-up wide-fan in domino logic using a controlled stro...

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International Conference on Computer and Communication Engineering, ICCCE

作者： Sherif M. Sharroush Yasser S. Abdalla Ahmed A. Dessouki El-Sayed A. El-Badawy Department of Elect Eng Engineering Suez-Canal University Port Said Egypt Department of Electricity Industrial Edu. Suez Canal University Suez Egypt Alex Higher Institute of Engineering and Tech & Engineering Alexandria University Alexandria Egypt

Wide fan in domino logic finds a variety of applications in microprocessors, digital signal processors, and dynamic memory. Specifically, there is a large number of applications that contain 8 or more transistors connected in parallel in the pull-down network (PDN) and thus the subthreshold leakage and charge sharing become severe. So, a strong PMOS keeper must be used in order to compensate for this leakage. However, the use of a strong keeper in the conventional domino circuit degrades the speed of the circuit considerably or results in an erroneous output. In this paper, a novel technique that acts to speed up the operation of wide fan in domino logic using a properly sized keeper is proposed. The keeper is controlled via a controlling cmos circuit. Some design issues of this technique such as the effect of the charge sharing on the operation of the proposed circuit and the size of the PMOS keeper will be discussed in this paper. Simulation will be carried out for the 0.13 mum technology with V DD =1.2 V for the case of 16 NMOS transistors in the PDN. Simulation results show the better noise immunity of the proposed circuit and the larger speed, however at the cost of increasing the area.

关键词： Circuit simulation Microprocessors Digital signal processors Subthreshold current Degradation cmos logic circuits cmos technology MOSFETs Circuit noise Costs

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A 32-bit carry lookahead adder design using complementary all-N-transistor logic

A 32-bit carry lookahead adder design using complementary al...

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IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Gang-Neng Sung Chun-Ying Juan Chua-Chin Wang Department of Electrical Engineering National Sun Yat-Sen University Kaohsiung Taiwan

A complementary all-N-transistor (CANT) comprising the ANT logic and a novel inverted ANT logic is proposed in this paper. The threshold voltage of the transistors in the ANT logicpsilas N-block is variable depending upon the operation of the entire logic block. In the evaluation phase, the bulk voltage of the transistors in the N-block is raised to VDD - Vthn such that the drain current therein is increased to enhance operation speed. In the pre-charge phase, the bulk voltage of those transistors in the N-block is reduced to its normal voltage level such that the subthreshold leakage current is dropped to reduce power consumption. By utilizing such a variable bulk voltage scheme in the CANT, a 32-bit CLA is designed to justify the low power and high speed performance. The power dissipation is 143 mW at 5.4 GHz clock rate given the worst PVT (SS, 1.08 V, 75degC) condition.

关键词： logic design Pulse inverters cmos logic circuits Clocks Power dissipation Pipeline processing logic circuits Threshold voltage Energy consumption Subthreshold current

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Multi-threshold cmos design for low power digital circuits

Multi-threshold CMOS design for low power digital circuits

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IEEE Region 10 International Conference TENCON

作者： S. Hemantha Amit Dhawan Haranath Kar Department of Electronics and Communication Engineering Motilal Nehru National Institute of Technology Allahabad India Department of Electronics and Communication Engineering Motilal Nehru National Institute of Technology Allahabad Allahabad India

Multi-threshold cmos (MTcmos) power gating is a design technique in which a power gating transistor is connected between the logic transistors and either power or ground, thus creating a virtual supply rail or virtual ground rail, respectively. Power gating transistor sizing, transition (sleep mode to active mode) current, short circuit current and transition time are design issues for power gating design. The use of power gating design results in the delay overhead in the active mode. If both nMOS and pMOS sleep transistor are used in power gating, delay overhead will increase. This paper proposes the design methodology for reducing the delay of the logic circuits during active mode. This methodology limits the maximum value of transition current to a specified value and eliminates short circuit current. Experiment results show 16.83% reduction in the delay.

关键词： cmos digital integrated circuits Digital circuits Delay Rails Short circuit currents cmos logic circuits logic design MOS devices Design methodology logic circuits

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