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检索条件"主题词=CMOS Logic Circuits"

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Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node

Experimental assessment of logic circuit performance variabi...

引用

European Conference on Solid-State circuits (ESSCIRC)

作者： Sungdae Choi Katsuyuki Ikeuchi Hyunkyung Kim Kenichi Inagaki Masami Murakata Nobuyuki Nishiguchi Makoto Takamiya Takayasu Sakurai University of Tokyo Japan Semiconductor Technology Academic Research Center Japan

Regular fabric structure is expected to reduce the process variations and increase the yield in sub-micron technology regime. Few experimental assessments, however, for the effectiveness of the regular structures has been carried out yet. In this paper, three kinds of circuit blocks are implemented with four kinds of layout styles with different regularity, and the effect of regularity on the circuit performance variations is evaluated. A test chip is fabricated with 90 nm cmos logic process and measured results show that the regular structure increases average delay, and the worst delay of the regular structure is not better than the worst delay of normal circuits with irregular standard cells.

关键词： logic circuits Fabrics cmos logic circuits Delay Circuit testing logic testing Circuit optimization cmos process Semiconductor device measurement Measurement standards

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Raising the Bar for Hardware Security: Physical Layer Security in Standard cmos

Raising the Bar for Hardware Security: Physical Layer Securi...

引用

IEEE Conference on Technologies for Homeland Security

作者： Craig Rawlings Kilopass Technology Inc.

As the sophistication of attacks on secured systems extends to the international electronic borders, there exists an increased need for enhanced physical layer security in silicon in order to protect sensitive information such as encryption keys used in most security systems. With hardware security as one of the new primary requirements for many, if not most, system architectures, new questions are being asked of various memory technologies in order to prohibit the reverse engineering or break down of the overall system for the life of that security system, standard, and/or protocol. One of the most relevant questions to the topic of hardware security is, "How physically secure is the underlying memory technology?" Equally important is the question of securing sensitive encryption keys throughout the manufacturing process. These two hardware security factors are important since encryption is only as robust as the ability for any encryption based system to keep the encryption key hidden. A new embedded permanent memory technology based on a standard logic cmos antifuse provides unprecedented physical layer security for security applications such as HDCP (High bandwidth Digital Content Protection) and AACS (Advanced Access Content System), both of which require unique encryption keys for each hardware device. While these are commercial security standards used to protect digital media in the consumer marketplace, the same principals apply to the public sector. A cmos logic antifuse technology, developed and patented by Kilopass, when combined with a robust key distribution, tracking, and management system, tailored for semiconductor manufacturing, provides end-to-end security for sensitive encryption keys from the author or originator of the encryption key through to the end product.

关键词： Hardware Physical layer Cryptography Information security Protection cmos technology Robustness cmos logic circuits logic devices Consumer electronics

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Using Implications for Online Error Detection

Using Implications for Online Error Detection

引用

IEEE International Test Conference

作者： K. Nepal N. Alves J. Dworak R. I. Bahar Electrical Engineering Department Bucknell University Lewisburg PA Division of Engineering Brown University Providence RI Division of Engineering Brown University Providence RI USA

In this paper, we investigate the use of logic implications for the online detection of intermittent faults and hard-to-detect manufacturing defects. We present techniques to efficiently identify the most powerful circuit implications that can be checked for violations so that the fraction of errors detected can be maximized while minimizing the additional hardware overhead. Importantly, our approach does not require re-synthesis of the targeted logic; the checker logic is added off the critical path and is run in parallel with the regular control logic. Trade-offs can be easily made between additional coverage of errors and additional area overhead. Our results show that significant error detection is possible - even with only a 10% area overhead.

关键词： Electrical fault detection Hardware Error correction Redundancy Power engineering and energy Circuit faults Pulp manufacturing cmos logic circuits cmos technology cmos process

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Power-delay optimization in MCML tapered buffers

Power-delay optimization in MCML tapered buffers

引用

IEEE International Symposium on circuits and Systems (ISCAS)

作者： Massimo Alioto Gaetano Palumbo Department of Information Engineering University of Sienna Siena Italy Department of Electrical Electronics and Systems Eng Universita Catania Catania Italy

In this paper, MOS current mode logic (MCML) tapered buffers are discussed from a design point of view. Closed-form design equations that relate the overall speed performance and the power consumption of MCML tapered buffers are derived for nanometer cmos technologies, i.e. by accounting for deep-sub-micron (DSM) effects from the beginning. The power-delay design space is then analytically explored, and design criteria are derived to properly size the number of stages and the current tapering factor under a speed/power constraint. The design criteria are simple enough to be used in pencil-and-paper calculations, as well as general and independent of the adopted technology. Hence, the proposed strategy provides the designer with an insight into the power-delay trade-off of MCML tapered buffers. Results are validated by means of simulations on a 90-nm cmos technology.

关键词： cmos logic circuits cmos technology Space technology Capacitance Semiconductor device modeling Energy consumption Timing Delay estimation Integrated circuit modeling Radio frequency

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A fully digital nonlinear, high-speed Rank Order Filter in 0.18μm cmos technology

A fully digital nonlinear, high-speed Rank Order Filter in 0...

引用

International Conference on Electrical and Computer Engineering (ICECE)

作者： George John Toscano Pran Kanai Saha American International University-Bangladesh Bangladesh Bangladesh University of Engineering and Technology Bangladesh

Some efficient techniques to realize modular, high-speed digital rank order filter (ROF) are presented in this paper. Using the proposed digital filters, it is possible to find the element of a certain rank (Maximum, Minimum and Median) in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed filters. The modified algorithm is implemented using N number of identical bit update circuit (BUC) along with other logic gates in 0.18 mum cmos technology. The proposed ROF circuits are simulated using HSPICE. Simulation results depict the good performance of the filters in terms of speed and power. The ROF algorithm is also tested in FPGA. The post fit simulation output using Xilinx is presented in this paper. In both simulations the ROFpsilas performance is gratifying.

关键词： cmos technology Digital filters Circuit simulation cmos logic circuits DH-HEMTs logic gates Circuit testing Field programmable gate arrays Algorithm design and analysis Nonlinear filters

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1V supply cmos DEMUX for 40-GB/S optical communication systems

1V supply CMOS DEMUX for 40-GB/S optical communication syste...

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Biennial Symposium on Communications, QBSC

作者： Bangli Liang Tad Kwasniewski Dianyong Chen Bo Wang Dezhong Cheng Department of Electronics Carleton University Ottawa ONT Canada

A 1 V supply 1:2 demultiplexer (DEMUX) based on 0.13 mum cmos technology is presented. It is designed for 40-Gb/s optical communication systems. This DEMUX achieved by a pair of master-slave flip-flops (MS-FFs) with opposite clock can operate at 40-Gb/s and beyond. Fully differential current mode logic (CML) is adopted to improve the bit rate of non-return-to-zero (NRZ) data stream and to suppress common mode disturbances. Output buffers for two outputs are employed to drive the external 50 Omega loads. On-chip shunt peaking (SP) inductors are used to boost the bandwidth. Stacked current source combined with low V T (LVT) and regular V T (RVT) NMOS is used so that the proposed DEMUX has good immunity against possible process, voltage and temperature (PVT) variations. This DEMUX IC dissipates a total current of 25 mA under a 1 V supply and consumes a chip area of 0.54 mm 2 with bonding pads.

关键词： Optical fiber communication cmos technology Optical design Master-slave Flip-flops Clocks cmos logic circuits Bit rate Optical signal processing Optical buffering

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Design of digitally controlled LC oscillator with wide tuning range in 0.18um TSMC cmos technology

Design of digitally controlled LC oscillator with wide tunin...

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Asia-Pacific Conference on Microwave

作者： Abhishek Tomar Ramesh Pokharel Haruichi Kanaya Keiji Yoshida Department of Electronics Graduate School of Information Science and Electrical Engineering Kyushu University Japan

Digitally controlled LC oscillator (LC-DCO) design in 0.18 mum cmos technology is presented with low phase noise and low power dissipation. Particular attention is given to achieve the wide tuning range. A varactor array is implemented using new logic, which made the significant reduction in the number of signal lines and the reduction in the size of local decoder, used to decode the input control word. This decoding scheme reduces the size of parasitic capacitance and power dissipation and provides wide tuning range of the proposed DCO.

关键词： cmos technology Digital control Oscillators Tuning Decoding Power dissipation logic arrays Phase noise Varactors cmos logic circuits

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3.1 GHz to 6 GHz UWB Pulse Radio Transceiver Front-End Based on Super-regeneration Approach

3.1 GHz to 6 GHz UWB Pulse Radio Transceiver Front-End Based...

引用

IEEE International Conference on Consumer Electronics (ICCE)

作者： M. Anis T. Ilnseher R. Tielert N. Wehn Institute of Microelectronic Technical University of Kaiserslautern Germany

This paper presents the UWB pulse radio transceiver front end based on multiple super regenerative receivers (SRR) tuned within UWB spectrum. The UWB signals are extracted in the presence of narrowband interfering channels like WLAN by logic redundancy check of all SRR outputs. The test structure of transceiver has been implemented on 0.18μm cmos technology, active area of 1.44 mm 2 , sensitivity of -90dBm, data exchange rate of 15Mbits/s with -30dB SIR, and power consumption of 1.5mW at 1.5V.

关键词： Radio transceivers cmos technology Receivers Data mining Narrowband Wireless LAN cmos logic circuits Testing Exchange rates Energy consumption

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Energy harvesting photodiodes with integrated 2D diffractive storage capacitance

Energy harvesting photodiodes with integrated 2D diffractive...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Nathaniel J. Guilar Erin G. Fong Travis Kleeburg Diego R. Yankelevich Rajeevan Amirtharajah Micropower Circuits and Systems Group University of California Davis CA

Integrating photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, low-cost energy harvesting wireless systems. To further explore the tradeoffs between optical efficiency and capacitive energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in TSMC's 90 nm cmos technology. Transient effects from interfacing the photodiodes with switching regulators were examined. A quantitative comparison between 90 nm and 0.35 μm cmos logic processes for energy harvesting capabilities was carried out. Measurements show an increase in power generation for the newer cmos technology, however at the cost of reduced output voltage.

关键词： Photodiodes Energy storage Capacitance cmos technology Optical diffraction cmos logic circuits Optical arrays Integrated optics Optical interconnections Photovoltaic cells

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A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for Blu-ray applications

A 125Mpixels/sec full-HD MPEG-2/H.264/VC-1 video decoder for...

引用

IEEE Asian Conference on Solid-State circuits (ASSCC)

作者： Chi-Cheng Ju Tsu-Ming Liu Yung-Chang Chang Chih-Ming Wang Hue-Min Lin Subrina Cheng Chun-Chia Chen Fred Chiu Kung-Sheng Lin Chung-Bin Wu Sling Liang Sheng-Jen Wang Ginny Chen T.C. Hsiao Chi-Hui Wang MediaTek Inc. Hsinchu Taiwan

A fully-compliant high-definition video decoder LSI for Blu-ray Disc (BD) player is presented. It supports MPEC-2 MP@HL, H.264 HP@L4.1, and VC-1 AP@L3 video decoding in a single chip and features resource sharing and memory management unit to achieve area/throughput efficiency. A test chip is fabricated and integrates 515 K logic gates with 522 Kbits of embedded SRAM in 90nm single-poly seven-metal cmos process with area of 5.06 mm 2 . For Blu-ray player requirements, video decoding of full 1920times1080 high-definition sequences at 60 frames per second requires 125 Mpixels/sec of processing throughput which is two times higher than comparable designs [5][6] and is achieved at 200 MHz clock frequency with power dissipation of 317 mW at 1.0 V supply voltage.

关键词： Decoding Video sharing High definition video Resource management Throughput logic testing Large scale integration Memory management logic gates cmos logic circuits

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