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检索条件"主题词=CMOS Logic Circuits"

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Co-integration of silicon nanodevices and NEMS for advanced information processing

Co-integration of silicon nanodevices and NEMS for advanced ...

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International Conference on Solid-State and Integrated Circuit Technology

作者： Hiroshi Mizuta Tasuku Nagami Jun Ogi Benjamin Pruvost Mario A. G. Ramirez Hideo Yoshimura Yoshishige Tsuchiya Shunri Oda NANO Group School of Electronics and Computer Science University of Southampton UK Quantum Nanoelectronics Research Center Tokyo Institute of Technology Japan Graduate School of Engineering Tokyo University of Agriculture슠and슠Technology Japan

ISBN: (纸本)9781424421855

In this paper we present our recent attempts at developing the advanced information processing devices by integrating nano-electro-mechanical (NEM) structures into conventional silicon nanodevices. Firstly, we show high-speed and nonvolatile NEM memory which features a mechanically-bistable floating gate is integrated onto MOSFETs. Secondly we discuss hybrid systems of single-electron transistors and NEM structures for exploring new switching principles.

关键词： Silicon Nanoelectromechanical systems Information processing Micromechanical devices cmos technology Nonvolatile memory Nanoscale devices Nanoelectronics MOSFETs cmos logic circuits

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Raising the Bar for Hardware Security: Physical Layer Security in Standard cmos

Raising the Bar for Hardware Security: Physical Layer Securi...

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IEEE Conference on Technologies for Homeland Security

作者： Craig Rawlings Kilopass Technology Inc.

As the sophistication of attacks on secured systems extends to the international electronic borders, there exists an increased need for enhanced physical layer security in silicon in order to protect sensitive information such as encryption keys used in most security systems. With hardware security as one of the new primary requirements for many, if not most, system architectures, new questions are being asked of various memory technologies in order to prohibit the reverse engineering or break down of the overall system for the life of that security system, standard, and/or protocol. One of the most relevant questions to the topic of hardware security is, "How physically secure is the underlying memory technology?" Equally important is the question of securing sensitive encryption keys throughout the manufacturing process. These two hardware security factors are important since encryption is only as robust as the ability for any encryption based system to keep the encryption key hidden. A new embedded permanent memory technology based on a standard logic cmos antifuse provides unprecedented physical layer security for security applications such as HDCP (High bandwidth Digital Content Protection) and AACS (Advanced Access Content System), both of which require unique encryption keys for each hardware device. While these are commercial security standards used to protect digital media in the consumer marketplace, the same principals apply to the public sector. A cmos logic antifuse technology, developed and patented by Kilopass, when combined with a robust key distribution, tracking, and management system, tailored for semiconductor manufacturing, provides end-to-end security for sensitive encryption keys from the author or originator of the encryption key through to the end product.

关键词： Hardware Physical layer Cryptography Information security Protection cmos technology Robustness cmos logic circuits logic devices Consumer electronics

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Power-delay optimization in MCML tapered buffers

Power-delay optimization in MCML tapered buffers

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Massimo Alioto Gaetano Palumbo Department of Information Engineering University of Sienna Siena Italy Department of Electrical Electronics and Systems Eng Universita Catania Catania Italy

In this paper, MOS current mode logic (MCML) tapered buffers are discussed from a design point of view. Closed-form design equations that relate the overall speed performance and the power consumption of MCML tapered buffers are derived for nanometer cmos technologies, i.e. by accounting for deep-sub-micron (DSM) effects from the beginning. The power-delay design space is then analytically explored, and design criteria are derived to properly size the number of stages and the current tapering factor under a speed/power constraint. The design criteria are simple enough to be used in pencil-and-paper calculations, as well as general and independent of the adopted technology. Hence, the proposed strategy provides the designer with an insight into the power-delay trade-off of MCML tapered buffers. Results are validated by means of simulations on a 90-nm cmos technology.

关键词： cmos logic circuits cmos technology Space technology Capacitance Semiconductor device modeling Energy consumption Timing Delay estimation Integrated circuit modeling Radio frequency

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A fully digital nonlinear, high-speed Rank Order Filter in 0.18μm cmos technology

A fully digital nonlinear, high-speed Rank Order Filter in 0...

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International Conference on Electrical and Computer Engineering (ICECE)

作者： George John Toscano Pran Kanai Saha American International University-Bangladesh Bangladesh Bangladesh University of Engineering and Technology Bangladesh

Some efficient techniques to realize modular, high-speed digital rank order filter (ROF) are presented in this paper. Using the proposed digital filters, it is possible to find the element of a certain rank (Maximum, Minimum and Median) in a given sequence of N elements in each window in M steps, where M is the number of bits used in binary representation for the elements of the sequence. A bit-level algorithm by Kar and Pradhan has been modified in this work to implement the proposed filters. The modified algorithm is implemented using N number of identical bit update circuit (BUC) along with other logic gates in 0.18 mum cmos technology. The proposed ROF circuits are simulated using HSPICE. Simulation results depict the good performance of the filters in terms of speed and power. The ROF algorithm is also tested in FPGA. The post fit simulation output using Xilinx is presented in this paper. In both simulations the ROFpsilas performance is gratifying.

关键词： cmos technology Digital filters Circuit simulation cmos logic circuits DH-HEMTs logic gates Circuit testing Field programmable gate arrays Algorithm design and analysis Nonlinear filters

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Memory design for high temperature radiation environments

Memory design for high temperature radiation environments

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Annual International Symposium on Reliability Physics

作者： Tai-Hua Chen Lawrence T. Clark Keith E. Holbert Department of Electrical Engineering Arizona State University Tempe AZ USA

This paper presents bulk cmos memory circuits capable of both ultra-low voltage (subthreshold, i.e., V DD less than the transistor threshold voltage V th ) low power operation and high temperature operation at nominal V DD . One of the memory designs is radiation hardened by design (RHBD) using interleaved DICE storage cells, enclosed transistor geometries, and P-type guard rings. The other is not hardened against radiation. Experimental results are presented showing that the room temperature minimum V DD of the hardened device remains essentially unchanged from the pre-irradiation V DDMIN = 210 mV value after Co-60 irradiation to 4 Mrad(Si). The standby power supply current I SB of the device increases less than 2x from this level of irradiation. The RHBD memory design has been tested to be operational at temperatures of 225degC. The combined effects of high temperature and irradiation are also investigated for both designs.

关键词： Photonic band gap Radiation hardening Temperature control Silicon on insulator technology Temperature distribution cmos logic circuits cmos memory circuits Threshold voltage Doping Monitoring

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Transistor sizing and layout merging of basic cells in pass transistor logic cell library

Transistor sizing and layout merging of basic cells in pass ...

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International Symposium on VLSI Design, Automation and Test

作者： Shen-Fu Hsiao Ming-Yu Tsai Chia-Sheng Wen Department of Computer Science and Engineering National Sun Yat-sen University Kaohsiung Taiwan

ISBN: (纸本)9781424416165

In the past two decades, pass transistor logic has been shown to have smaller power and area cost compared to traditional cmos logic for some applications. Some important issues related to the design of pass transistor cell library are discussed in this paper. First, the transistor sizing for the special inverter circuit in the cell library is addressed, which is quite different from the sizing of conventional cmos inverter. Second, we create new cells that merge combinations of an inverters and some multiplexers in order to reduce the physical layout area. Experimental results show that the layout compaction method also reduces the delay and dynamic power. The proposed transistor sizing and layout compaction methods could be useful guidelines in designing the basic cells required in pass-transistor logic synthesis.

关键词： Merging Libraries cmos logic circuits Inverters Compaction Costs Multiplexing Delay Guidelines logic design

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Design for testability for SoC based on IDDQ scanning

Design for testability for SoC based on IDDQ scanning

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International Conference on Microelectronics, MIEL

作者： Miljana Sokolovic Predrag Petkovic Vanco Litovski Department of Electronics Faculty of Electronic Engineering University of Nis Serbia

One DFT solution for systems on chip, based on IDDQ measuring concept is presented in this paper. The application of Reconfigurable neurai networks off chip enables also good diagnostics capabilities. The solution is to be implemented in few digital blocks of the tree phase power meter IC and realized using cmos035 technology. The simulation results obtained using Cadence Virtuoso show good performances of the solution.

关键词： Design for testability Circuit testing Circuit faults Electronic equipment testing cmos integrated circuits Current measurement Fault detection Integrated circuit measurements cmos logic circuits Observability

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Energy harvesting photodiodes with integrated 2D diffractive storage capacitance

Energy harvesting photodiodes with integrated 2D diffractive...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Nathaniel J. Guilar Erin G. Fong Travis Kleeburg Diego R. Yankelevich Rajeevan Amirtharajah Micropower Circuits and Systems Group University of California Davis CA

Integrating photodiodes with logic and exploiting on-die interconnect capacitance for energy storage can enable new, low-cost energy harvesting wireless systems. To further explore the tradeoffs between optical efficiency and capacitive energy storage for integrated photodiodes, an array of photovoltaics with various diffractive storage capacitors was designed in TSMC's 90 nm cmos technology. Transient effects from interfacing the photodiodes with switching regulators were examined. A quantitative comparison between 90 nm and 0.35 μm cmos logic processes for energy harvesting capabilities was carried out. Measurements show an increase in power generation for the newer cmos technology, however at the cost of reduced output voltage.

关键词： Photodiodes Energy storage Capacitance cmos technology Optical diffraction cmos logic circuits Optical arrays Integrated optics Optical interconnections Photovoltaic cells

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Impact of technology scaling on the performance of domino cmos logic

Impact of technology scaling on the performance of domino CM...

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International Conference on Electronic Design (ICED)

作者： Sherif M. Sharroush Yasser S. Abdalla Ahmed A. Dessouki El-Sayed A. El-Badawy Department of Elect Eng Fac. of Engineering Suez Canal University Egypt Department of Electricity Fac. of Industrial Edu. Suez Suez Canal University Egypt Alex Higher Institute Of Engineering and Tech & Fac. of Engineering Aexaadria University Alexandria Egypt

Domino cmos logic circuit family finds a wide variety of applications in microprocessors, digital signal processors, and dynamic memory due to their high speed and low device count. However, there are inevitable problems that degrade the noise immunity of this family; they are the inevitable leakage current and the charge sharing. Added to the drawbacks is the relatively large power consumption, especially if compared to the static complementary cmos logic family. To make the matter worse, these drawbacks are more tactile with the scaling of cmos technology from one generation to the next. In this paper, the impact of cmos technology scaling on the performance of domino cmos logic will be investigated. Specifically, the need to decrease the dynamic power consumption forces the designer to use a lower power-supply voltage. This in turn necessitates the reduction of threshold voltage to maintain the performance with the associated increase in subthreshold leakage current. So, a properly sized PMOS keeper must be used to compensate for this leakage. It will be found that the speed, which is the major advantage of domino logic compared to other logic styles, will degrade with cmos technology scaling due to the contention current of the keeper. A technique that extends the life time of domino logic in spite of cmos technology scaling will be proposed. In fact, this technique aims to alleviate the effects of threshold-voltage reduction and the associated increase in subthreshold leakage on the noise immunity and the size of the PMOS keeper through the use of a current sensing circuit. This technique will be simulated for the 0.13 mum technology with power-supply voltage, V DD =1.2 V. Simulation results show that the proposed technique enhances the noise margin by approximately 560 mV and enhances the speed by approximately 56% compared to the conventional technique in which the gate of the PMOS keeper is connected to the output terminal, however, at the cost of an area pe

关键词： cmos technology cmos logic circuits Circuit noise logic devices Degradation Energy consumption Subthreshold current Circuit simulation Microprocessors Digital signal processors

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5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk cmos

5.75 to 44Gb/s quarter rate CDR with data rate selection in ...

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European Conference on Solid-State circuits (ESSCIRC)

作者： George von Bueren Lucio Rodoni Heinz Jaeckel Roland Brun Daniel Holzer Alex Huber Martin Schmatz Electronics Laboratory ETH Zürich Zurich Switzerland Institute of MicroElectronics University of Applied Science Windisch Switzerland Bern University of Applied Sciences Burgdorf Switzerland IBM Zurich Research Laboratory Switzerland

This paper presents a quarter rate clock/data recovery (CDR) circuit for plesiochronous serial I/O-links. This 2x-oversampled phase-tracking CDR, implemented in 90 nm bulk cmos technology, covers the whole range of data rates from 5.75 to 44 Gb/s thanks to a data rate selection logic. A bit error rate <10 -12 was verified up to 38 Gb/s using a 2 7-1 PRBS pattern. The CDR is able to track a maximum frequency deviation of plusmn615 ppm between incoming data and reference clock.

关键词： Clocks Frequency cmos technology cmos logic circuits Bit error rate Digital filters Tracking loops Laboratories Energy consumption cmos process

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