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检索条件"主题词=CMOS Logic Circuits"

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Minimization of energy dissipation in glitch free and cascadable adiabatic logic circuits

Minimization of energy dissipation in glitch free and cascad...

引用

IEEE Region 10 International Conference TENCON

作者： N. Siva Sankara Reddy M. Satyam K. Lal Kishore Vasavi College of Engineering Hyderabad Andhra Pradesh India Indian Institute of Information Technology Hyderabad India J.N.T. University Hyderabad India

The energy dissipation in the logic circuits can be reduced by using adiabatic techniques. In this paper, we describe a technique for further reduction in energy dissipation in glitch free and cascadable adiabatic logic (GFCAL) circuits by using two complementary supply waveforms and single input signal. Measurements of energy drawn, energy recovered and dissipated have been carried out through simulation. The reduction in energy dissipation in the inverter proposed is about 65 percent compared to that of standard cmos, up to 1000 MHZ.

关键词： Minimization Energy dissipation logic circuits Clocks Diodes Capacitors cmos logic circuits Voltage Power dissipation MOSFET circuits

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Low-leakage and low-power implementation of high-speed 65nm logic gates

Low-leakage and low-power implementation of high-speed 65nm ...

引用

IEEE Conference on Electron Devices and Solid-State circuits

作者： Tsung-Yi Wu Liang-Ying Lu Cheng-Hsun Liang Department of Electronic Engineering National Changhua University of Education Taiwan

In this paper, we propose novel transmission-gate-based (TG-based) AND gates, TG-based OR gates, and pass-transistor logic gates that have new structures and have lower transistor counts than those proposed by other authors. All our proposed gates operate in full swing and have less leakage currents, less dynamic power consumption, and shorter delays than conventional cmos gates. Compared with the conventional 65 nm cmos gates, our proposed 65 nm gates can improve leakage currents, dynamic power consumption, and propagation delays by averages of 29.5%, 15.3%, and 30.3%, respectively. logic synthesizers can use our proposed gates to facilitate power reduction. The experimental results show that Power Compiler can further reduce the leakage current and dynamic power up to 35.0% and 20.0%, respectively, when the standard cell library used by Power Compiler contains our proposed gates.

关键词： logic gates Leakage current cmos logic circuits Energy consumption Subthreshold current Threshold voltage cmos technology Propagation delay MOSFET circuits Synthesizers

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RF Design of On-Chip EMI Filters in cmos logic IC

RF Design of On-Chip EMI Filters in CMOS Logic IC

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European Conference on Microwave

作者： Shigeru Hiura Takaya Kitahara Yutaka Oohashi Corporate Manufacturing Engineering Center Toshiba Corporation Japan Semiconductor Company Toshiba Corporation Japan

In this paper, we present new design methods that provide the radio frequency (RF) rejection performance of on-chip electromagnetic interference (EMI) filters in a complementary metal-oxide semiconductor (cmos) logic integrated circuit (IC). In order to simulate on-chip performance, we consider the following concepts. Firstly, simulation models consist of simulation program with integrated circuit emphasis (SPICE) models of logic circuits, an IC chip design, an IC package design and a printed circuit board (PCB) design. Secondly, RF rejection performance is obtained using a frequency domain analysis of output data signals from ICs including and excluding EMI filters. Simulation results show that an on-chip-type EMI filter has better performance in the frequency band for wireless communications than other types of EMI filter. The measurement results show good agreement with the simulation results.

关键词： Radio frequency Electromagnetic interference Filters cmos logic circuits logic design cmos integrated circuits Radiofrequency integrated circuits Integrated circuit modeling Circuit simulation Semiconductor device modeling

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Development of passive devices in 130 nm RFcmos technology and PDK implementation for RF VCO designs

Development of passive devices in 130 nm RFCMOS technology a...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Xinzhong Duo Tinghuang Lee Paul Wen Lindsay Kang Tweeg Chen Paul Zhu Li-Wu Yang Semiconductor Manufacturing International Corporation Shanghai China

ISBN: (纸本)9781424421855

This paper focuses on the design of RF component design such as MOSFETs, varactors, capacitors and inductors in SMIC 0.13 ¿m RFcmos technology. Modeling results of these passives devices and associated PDK are implemented in a 0.13 ¿m RFcmos VCO design. The RF building block has been fabricated from 130 nm cmos technology and achieved a phase noise of -140.8 dBc/Hz@1 MHz at a current consumption of 14 mA.

关键词： Radio frequency Voltage-controlled oscillators MOSFETs Varactors cmos technology Q factor Inductors cmos logic circuits Fingers Semiconductor device noise

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Computation with Energy-Time Trade-Offs: Models, Algorithms and Lower-Bounds

Computation with Energy-Time Trade-Offs: Models, Algorithms ...

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International Symposium on Parallel and Distributed Processing with Applications, ISPA

作者： Brad D. Bingham Mark R. Greenstreet Department of Computer Science University of British Columbia Vancouver BC Canada

Power consumption has become one of the most critical concerns for processor design. This motivates designing algorithms for minimum execution time subject to energy constraints. We propose simple models for analysing algorithms that reflect the energy-time trade-offs of cmos circuits. Using these models, we derive lower bounds for the energy-constrained execution time of sorting, addition and multiplication, and we present algorithms that meet these bounds. We show that minimizing time under energy constraints is not the same as minimizing operation count or computation depth.

关键词： Algorithm design and analysis Computational modeling Concurrent computing Semiconductor device modeling Programming profession cmos logic circuits Voltage Parallel processing Topology Sorting

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cmos bulk input current switch logic circuit

CMOS bulk input current switch logic circuit

引用

IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Hong-Yi Huang Chun-Tsai Hung Sheng-Chia Chiang Graduate Institute of Electrical Engineering National Taipei University Taiwan Department of Electronic Engineering National ShaLu Industrial Vocational Senior High School Taiwan

In this work, the cmos bulk-input current switch logic (BCSL) circuit is proposed. A negative (positive) boost circuit providing a voltage level for NMOS (PMOS) bulk terminal is also developed to avoid the forward biasing of drain/source-to-bulk junctions. A current latch sense amplifier is used to generate a pair of full-swing output signals without dc power dissipation. The devices in the differential logic network are connected in parallel, leading to low parasitic resistive and capacitive load. The dynamic power is reduced. The BCSL has the potential of low-power and high-speed operation in low-voltage design. It is shown that the BCSL has better speed and power performance compared to the conventional differential logic circuits in simulation results.

关键词： Switches cmos logic circuits Switching circuits logic circuits Voltage MOS devices Latches Power amplifiers DC generators Power generation

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A 2-Bit 4GS/s flash A/D converter in 0.18 μm cmos for an IR-UWB communication system

A 2-Bit 4GS/s flash A/D converter in 0.18 μm CMOS for an IR...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Canxing Lu Lu Huang Wenjia Li Department of Electronic Science and Technology University of Science and Technology Hefei Anhui China

ISBN: (纸本)9781424421855

A 4 GS/s 2-bit non-time-interleaved flash ADC is designed for an IR-UWB (Impulse Radio Ultra Wide Band) receiver. In this flash ADC, implementing differential low-swing operation in analog part and CML (current mode logic) in digital part result in high-speed and low power consumption. Furthermore, because of the low-bit-sampling characteristic of the IR-UWB system, non-time-interleaved structure is used without digital calibration which largely saves the power consumption, chip area and cost. And a differential resistive reference ladder is designed to minimize the inaccuracy of the reference voltage. The proposed ADC dissipates 34 mW power from a 1.8 V supply while operating at 4 GHz. This chip has been fabricated in 0.18 μm 1P6M cmos process and the ADC achieves 1.86-bit effective number of bits (ENOB) for input signal of 1 GHz at 4 GS/s in simulation of FFT analysis.

关键词： Energy consumption Ultra wideband technology Receivers cmos logic circuits Calibration Costs Voltage cmos process Signal processing Analytical models

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Modeling of Substrate Noise Effects in Dynamic cmos circuits

Modeling of Substrate Noise Effects in Dynamic CMOS Circuits

引用

IEEE Region 5 Annual Technical Conference

作者： Sagar. R. Gosavi Waleed K. Al-Assadi Sasikiran Burugapalli Department of Electrical and Computer Engineering Missouri University of Science and Technology Rolla MO USA

The decrease in the feature size has led to the integration of both digital and analog circuits on the same silicon die which has led to many crosstalk issues. The crosstalk due to the substrate interactions also plagiarizes complete digital systems. This paper lays emphasis on this fact and because of the vulnerability of dynamic cmos circuits to noise; a brief study of the effects of substrate variations on the performance of the dynamic cmos circuits is carried out in this paper. The effects of substrate noise at very high frequencies (above 10 GHz) are also depicted in this paper. In order to accurately estimate the effects of substrate noise a substrate model is proposed and verified for functionality in the last section of this paper.

关键词： Semiconductor device modeling Circuit noise Crosstalk Coupling circuits Threshold voltage logic circuits Frequency cmos logic circuits Analog circuits Digital systems

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Technologies and materials for memory with full compatibility to cmos

Technologies and materials for memory with full compatibilit...

引用

International Conference on Solid-State and Integrated Circuit Technology

作者： Min-hwa Chi HanMing Wu SOC Technology Development Semiconductor Manufacturing International (Shanghai) Corp. Shanghai P.R.C.

As cmos scaling continuous successfully, technologies for integrating both memory and logic together is highly desirable for high performance and low-power system-on-chip (SOC) with full cmos compatibility, such as logic based NVM, floating-body DRAM, MiM based eDRAM, PC-RAM, RRAM, MRAM, FeRAM, ...etc.. New materials (e.g. GST, metal-oxide, high-k, magnetic junction, ...etc.) have greater compatibility in BEOL. Thus, fully cmos compatible SOC is a promising trend into the future.

关键词： cmos technology Random access memory Nonvolatile memory High-K gate dielectrics MIM capacitors cmos logic circuits High K dielectric materials Tunneling SONOS devices Channel hot electron injection

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Fault-Tolerant Computing Using a Hybrid Nano-cmos Architecture

Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architectu...

引用

International Conference on VLSI Design

作者： Muzaffer O. Simsir Srihari Cadambi Franjo Ivancic Martin Roetteler Niraj K. Jha Princeton University Princeton NJ USA NEC Labs America Princeton NJ USA

ISBN: (纸本)9780769530833;0769530834

Architectures based on nanoscale molecular devices are attracting attention for replacing cmos architectures at the end of the semiconductor roadmap. The two most promising nanotechnologies, according to ITRS, are silicon nanowires and carbon nanotubes. Although they offer unmatched densities for building logic, interconnect and memory, they suffer from very defect-prone manufacturing processes. This is further exacerbated by testing complexities where it is nearly impossible to detect all defects in a large nanoscale chip. Furthermore, the small structures in nanoscale architectures are susceptible to transient faults which can produce arbitrary soft errors. As a result, fault tolerance is necessary to make nanoscale architectures practical and realistic. We propose an architecture that can tolerate a large number of undetected manufacturing faults as well as a large rate of transient faults. Our architecture is characterized by multiple levels of redundancy and majority voting to correct errors caused by such faults. A key aspect of the architecture is that it contains a judicious balance of both nanoscale and traditional cmos components. A companion to the architecture is a compiler with heuristics tailored to quickly and compactly map logic onto partially defective components. Experimental results demonstrate the efficacy of the architecture.

关键词： Fault tolerance Computer architecture cmos logic circuits Nanoscale devices Silicon Nanowires Carbon nanotubes Buildings logic devices Manufacturing processes

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