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检索条件"主题词=CMOS Logic Circuits"

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Minimum power-delay product design of MCML gates

Minimum power-delay product design of MCML gates

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International Conference on Signals and Electronic Systems, ICSES

作者： Giuseppe Caruso Alessio Macchiarella Dipartimento di Ingegneria Elettrica Elettronica e delle Telecomunicazioni Università di Palermo Palermo Italy Dipartimento di Fisica della Materia e Tecnologie Fisiche Avanzate University of Messina Messina Italy

This paper describes a methodology for the minimization of the power-delay product of MCML gates. The method is based on the novel concept of crossing point capacitance. The methodology was been validated by designing... 详细信息

关键词： Product design Parasitic capacitance Delay MOSFETs Voltage cmos logic circuits Resistors Telecommunications Minimization methods cmos process

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A 4GHz direct digital frequency synthesizer utilizing a nonlinear sine-weighted DAC in 90nm cmos

A 4GHz direct digital frequency synthesizer utilizing a nonl...

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IEEE Asia-Pacific Conference on circuits and Systems

作者： Hong Chang Yeoh Kwang-Hyun Baek Department of Electrical and Electronic Engineering Chung-Ang University Seoul South Korea

A nonlinear sine-weighted digital-to-analog converter (DAC) can significantly reduces the power consumption and the complexity of direct digital frequency synthesizers (DDFSs). With the sine conversion implemented in the DAC, the phase-to-amplitude mapping (PAM) stage can be totally eliminated, thus drastically reduces the latency and increases the speed of the DDFS as the PAM stage is usually the speed bottleneck of a DDFS design. Utilizing quarter wave mapping technique, the simulated results of the DDFS with a 7-bit sine approximation using a modified binary-to-thermometer decoder, current switch and driver achieve a maximum spurious free dynamic range (SFDR) of 53 dBc at low synthesized output and better than 44 dBc across the whole Nyquist range when clocked at 4 GHz. Designed and simulated in 90 nm cmos, this monolithic DDFS has 6 clock cycle latency and consumes only 462 mW when operating at 4 G sample/s.

关键词： Frequency synthesizers Clocks Read only memory Delay Switches Energy consumption Phase locked loops cmos logic circuits Digital-analog conversion Communication switching

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Investigation of the influence of process and design on soft error rate in integrated cmos technologies thanks to Monte Carlo simulation

Investigation of the influence of process and design on soft...

引用

Annual International Symposium on Reliability Physics

作者： C. Weulersse A. Bougerol G. Hubert F. Wrobel T. Carriere R. Gaillard N. Buard EADS-IW Suresnes France ONERA Toulouse France EADS-IW France IES Montpellier France EADS Astrium GmbH France INFODUC Igny France

This work shows the capabilities of Monte Carlo simulation based on nuclear database to identify the influence of device parameters and process on Single Cell Upset and Multicell Upset rates in integrated bulk and SOI cmos technologies up to 65 nm. The method is applicable both to SRAM and logic cells, and is valid for high energy and thermal neutrons.

关键词： cmos technology Process design Error analysis cmos process Neutrons Random access memory Sliding mode control Databases cmos logic circuits Silicon on insulator technology

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High Speed Ultra Low Voltage cmos inverter

High Speed Ultra Low Voltage CMOS inverter

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IEEE Computer Society Annual Symposium on VLSI

作者： Yngvar Berg Omid Mirmotahari Johannes Goplen Lomsdalen Snorre Aunet Department of Informatics University of Oslo Oslo Norway

In this paper we discuss timing details and performance of the ultra low voltage (ULV) logic style. The ULV logic gates can be utilized to design high speed systems operating at ultra low supply voltages. By imposing offsets to semi-floating-gate nodes the current level may be increased while maintaining a very low supply voltage. The offsets voltages are used to shift the effective threshold voltage of the evaluating transistors. The simulated data presented is obtained using the Spectre simulator provided by Cadence and valid for a 90 nm cmos process.

关键词： Low voltage Inverters Threshold voltage cmos logic circuits Energy consumption Circuit simulation cmos process Circuit synthesis Leakage current cmos technology

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A New Domino logic Synthesis Approach

A New Domino Logic Synthesis Approach

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International Conference on Internet Computing in Science and Engineering (ICICSE)

作者： Xiaoxiao Liu Tao Zhou Jingbo Shao Haijun Li Huiling Lu College of Computer Science&Technology Harbin Engineering of Technology Harbin China Department of Maths Shaanxi University of Technology Hanzhong China Department of Computer Science Shaanxi University of Technology Hanzhong China

Domino logic is the most popular dynamic logic, but the high crosstalk noise, area and power penalties limit its application. In this paper, a new domino logic synthesis approach was proposed, which considered all the crosstalk immunity of OR gate, low switching activity of AND gate, and post-layout logic optimization. Experimental results show that our algorithm can effectively reduce crosstalk noise and area overhead while maintaining low power.

关键词： Crosstalk Pulse inverters cmos logic circuits logic circuits Observability cmos digital integrated circuits Capacitance Power dissipation Network synthesis Internet

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Device design tradeoffs for 55v ldmos driver embedded in 0.18 micron platform

Device design tradeoffs for 55v ldmos driver embedded in 0.1...

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IEEE Convention of the Electrical and ELectronic Engineers in Israel

作者： Nathanaelle Klein Sharon Levin Gal Fleishon Sagy Levy Alon Eyal Shye Shapira Tower Semiconductor Limited Israel

We describe the optimization of a 55 V breakdown LDMOS embedded in a 0.18 micron based power management platform. The devices self aligned structure allow the accessing low RdsOn values of 50 mohm mm 2 . We focus on the effects of gate poly over STI overlap which can increase the breakdown voltage by 10 V and reduce maximum substrate current 5 fold while not affecting the specific RdsOn.

关键词： Implants Energy management cmos process cmos logic circuits Poles and towers Aluminum Metal-insulator structures logic devices Breakdown voltage Immune system

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Low-power “Smart” cmos image sensors

Low-power “Smart” CMOS image sensors

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Alexander Fish Orly Yadid-Pecht Department of Electrical and Computer Engineering University of Calgary AB Canada The VLSI Systems Center Ben-Gurion University of the Negev Beersheba Israel

Fast development of low-power miniature cmos sensors triggers their penetration to various applications, such as bio-medical applications, digital still and video cameras, cellular phones, web and security cameras and many other applications. The advantages of cmos imagers over conventional CCD sensors are the possibility in integration of all functions required for timing, exposure control, color processing, image enhancement, image compression, analog-to-digital (ADC) conversion on the same chip and low-power operation. However, although cmos imagers naturally provide low-power dissipation, their wide utilization in various portable battery-operated devices generates an increased demand for more aggressive power reduction. This paper presents a "smart" image sensor architecture and reviews general considerations for power reduction in cmos image sensors at all possible design levels - technology, device, circuit, logic, architecture, algorithm and system integration.

关键词： cmos image sensors Biosensors Digital cameras cmos logic circuits Video compression Cellular phones Security cmos process Charge coupled devices Charge-coupled image sensors

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A low power, process invariant keeper for high speed dynamic logic circuits

A low power, process invariant keeper for high speed dynamic...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： David J. Rakesh Gnana Navakanta Bhat Department of Electrical Communication Engineering Indian Institute of Science Bangalore 560012 India Department of Electrical Communication Engineering Indian Institute of Science Bangalore India

A low power keeper circuit using the concept of rate sensing has been proposed. The proposed technique reduces the amount of short circuit power dissipation in the domino gate by 70% compared to the conventional keeper technique. Also the total power-delay product is 26% lower compared to the previously reported techniques. The process tracking capability of the design enables the domino gate to achieve uniform delay across different process corners. This reduces the amount of short circuit power dissipation that occurs in the cascaded domino gates by 90%. The use of the proposed technique in the read path of a register file reduces the energy requirement by 26% as compared to the other keeper techniques. The proposed technique has been prototyped in 130 nm cmos technology.

关键词： logic circuits Power dissipation Delay Noise robustness Circuit noise MOS devices cmos logic circuits Inverters Power engineering and energy cmos technology

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A low-cost realization of quantum ternary adder using muthukrishnan-stroud gate

A low-cost realization of quantum ternary adder using muthuk...

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International Conference on Electrical and Computer Engineering (ICECE)

作者： Md. Mehedi Hasan Department of Electrical and Electronic Engineering Bangladesh University of Engineering and Technology Dhaka Bangladesh

Ternary quantum computing technology is a promising technology for future computer systems. In any computer system, an adder circuit is an essential circuit that performs arithmetic and logic operation of the computer. So, for the ternary quantum computer system, an efficient and low-cost realization of ternary adder is very necessary. This paper introduces a novel realization of quantum ternary adder which reduces the realization cost extensively compared to the previous realization.

关键词： Quantum computing Adders Multivalued logic Costs logic circuits DH-HEMTs Computers cmos logic circuits Circuit synthesis Arithmetic

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Analysis of the impact of process variations on static logic circuits versus fan-in

Analysis of the impact of process variations on static logic...

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IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Massimo Alioto Gaetano Palumbo Melita Pennisi DII-Department of Information Engineering University of Sienna Siena Italy DIEES Universita Catania Catania Italy

In this paper, the effect of process variations on the delay of cmos static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor size. Theoretical results are useful to gain an insight into the dependence of the delay variation on design parameters. Monte Carlo simulations on a 90-nm technology were performed to validate the results.

关键词： logic circuits Delay effects logic gates Analytical models Power supplies Integrated circuit technology Intrusion detection Wire Information analysis cmos logic circuits

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