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检索条件"主题词=CMOS Logic Circuits"

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Analysis of the impact of process variations on static logic circuits versus fan-in

Analysis of the impact of process variations on static logic...

引用

IEEE International Conference on Electronics, circuits and Systems (ICECS)

作者： Massimo Alioto Gaetano Palumbo Melita Pennisi DII-Department of Information Engineering University of Sienna Siena Italy DIEES Universita Catania Catania Italy

In this paper, the effect of process variations on the delay of cmos static logic circuits is discussed versus fan-in. In particular, the effect of process variations in stacked transistors (which determine the fan-in) is analytically evaluated. From circuit analysis, a simple analytical model is derived that expresses the delay variation as a function of the number of stacked transistors and transistor size. Theoretical results are useful to gain an insight into the dependence of the delay variation on design parameters. Monte Carlo simulations on a 90-nm technology were performed to validate the results.

关键词： logic circuits Delay effects logic gates Analytical models Power supplies Integrated circuit technology Intrusion detection Wire Information analysis cmos logic circuits

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Correlation verification between transistor variability model with body biasing and ring oscillation frequency in 90nm subthreshold circuits

Correlation verification between transistor variability mode...

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International Symposium on Low Power Electronics and Design (ISLPED)

作者： Hiroshi Fuketa Masanori Hashimoto Yukio Mitsuyama Takao Onoye Osaka Daigaku Suita Osaka JP

This paper presents modeling of manufacturing variability and body bias effect for subthreshold circuits based on measurement of a device array circuit in a 90 nm technology. The device array consists of P/NMOS transistors and ring oscillators. This work verifies the correlation between the variation model extracted from IV measurement results and oscillation frequencies, which means the transistor-level variation model is examined and confirmed in terms of circuit performance. We demonstrate that delay variations of subthreshold circuits are well characterized with two parameters - threshold voltage and subthreshold swing parameter. We reveal that body bias effect is a less statistical phenomenon and threshold voltage shift by body biasing can be modeled deterministically.

关键词： MOSFETs Frequency measurement Threshold voltage Manufacturing Delay cmos logic circuits Subthreshold current Ring oscillators Integrated circuit measurements logic devices

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Tessellation-enabled shader for a bandwidth-limited 3D graphics engine

Tessellation-enabled shader for a bandwidth-limited 3D graph...

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Custom Integrated circuits Conference (CICC)

作者： Kyusik Chung Chang-Hyo Yu Donghyun Kim Lee-Sup Kim Department of EECS KAIST Daejeon South Korea

A tessellation-enabled shader (TES), 1/250 memory bandwidth saving geometry processor, is proposed for a mobile 3D graphics engine. By utilizing operational characteristic of tessellation, the TES is implemented with 6.2% additional logic of a dedicated unit based on a conventional vertex shader. With optimization of key components of a shader, a symmetric dual-core TES is fabricated using 0.18 um cmos technology and processes 120 Mvertices/s at 100 MHz while consuming 272 mW of power.

关键词： Graphics Engines Bandwidth cmos technology System-on-a-chip Geometry Multimedia systems logic arrays cmos logic circuits cmos process

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cmos Control Enabled Single-Type FET NASIC

CMOS Control Enabled Single-Type FET NASIC

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IEEE Computer Society Annual Symposium on VLSI

作者： Pritish Narayanan Michael Leuchtenburg Teng Wang Csaba Andras Moritz University of Massachusetts Amherst MA USA

A new hybrid cmos-nanoscale circuit style has been developed that uses only one type of Field Effect Transistor (FET) in the logic portions of a design. This is enabled by cmos providing control signals that coordinate the operation of the logic implemented in the nanoscale. In this paper, the new circuit style is explored, examples from a microprocessor design are shown, performance, manufacturing and density implications discussed. The system is based on the existing cmos-nano hybrid fabric architecture NASIC, but the new circuit style reduces the requirements on devices and manufacturing from previous NASIC designs, significantly improves performance without any deterioration in circuit density.

关键词： FETs cmos logic circuits Fabrics Tiles Semiconductor device manufacture logic devices logic design Nanowires Nanoscale devices MOS devices

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A 3.6pW/frame·pixel 1.35V PWM cmos Imager with Dynamic Pixel Readout and no Static Bias Current

A 3.6pW/frame·pixel 1.35V PWM CMOS Imager with Dynamic Pixe...

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IEEE International Conference on Solid-State circuits (ISSCC)

作者： Keiichiro Kagawa Sanshiro Shishido Masahiro Nunoshita Jun Ohta Osaka University Suita Japan Nara Institute of Science and Technology Ikoma Japan

ISBN: (纸本)9781424420100

Low-power operation of cmos imagers using a low voltage (around IV or less) compatible with deep submicron logic circuits enables new imager applications, such as disposable medical cameras and autonomous wireless security cameras on a chip. Pulse width modulation (PWM) is promising for this purpose. A PWM pixel can convert light intensity to a digital pulse width by using an in-pixel comparator with a low power-supply voltage without any degradation of signal-to-noise ratio (SNR). In this paper, we propose and demonstrate a low-power dynamic pixel readout in-pixel comparators(DPR) scheme with CGA PWM pixels based on dynamic operation of in-pixel comparators. DPR requires no static bias current even in the pixel readout. The power dissipation of the pixel array is dramatically reduced by 1 to 2 orders of magnitude compared with using normal static pixel readout (SPR).

关键词： Pulse width modulation Pixel Low voltage cmos image sensors Cameras Space vector pulse width modulation cmos logic circuits logic circuits Biomedical imaging Communication system security

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A Novel ATPG Framework to Detect Weight Related Defects in Threshold logic Gates

A Novel ATPG Framework to Detect Weight Related Defects in T...

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26th IEEE VLSI Test Symposium (VTS 2008)

作者： Manoj Kumar Goparaju Spyros Tragoudas Department of Electrical and Computer Engineering Southem Illinois University Carbondale Carbondale IL USA

The gate that is implemented with threshold logic is called a Threshold logic Gate (TLG). The logic output value of an TLG depends on the weighted sum of its inputs. Manufactured weights in the threshold logic gates (TLGs) may differ from the designed values and significantly affects the fault coverage. A novel Automatic Test Pattern Generation (ATPG) tool is proposed to detect whether the circuit is malfunctioning due to such weight-related defects.

关键词： Automatic test pattern generation logic gates logic devices logic testing Circuit faults cmos logic circuits Manufacturing cmos technology Very large scale integration logic design

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Technology Features and Design Tools for mm-wave Applications in cmos

Technology Features and Design Tools for mm-wave Application...

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European (Formerly European Gallium Arsenide and Other Semiconductors Application Symposium - EGASS) Microwave Integrated Circuit Conference (EuMIC)

作者： John J. Pekarik IBM Semiconductor Research and Development Center Crolles France

Leading-edge cmos provides transistor performance that, by traditional measures, is more than adequate for implementing millimetre-wave transceivers. Analogue and RF design is supported by device-level libraries and e... 详细信息

关键词： cmos technology Very large scale integration Tensile strain Uniaxial strain Silicon germanium Germanium silicon alloys Radio frequency cmos logic circuits logic design Design methodology

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Single-phase power-gating adiabatic flip-flops

Single-phase power-gating adiabatic flip-flops

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IEEE Asia-Pacific Conference on circuits and Systems

作者： Hong Li Lifang Ye Jinghong Fu Jianping Hu Faculty of Information Science and Technology Ningbo University Ningbo Zhejiang China

This paper presents low-power power-gating adiabatic flip-flops using single-phase power-clock scheme. The proposed power-gating adiabatic flip-flops are realized with improved CAL (Clocked Adiabatic logic) circuits. The refresh enable terminals are added for power-gating operation. A power-gating scheme for the single-phase adiabatic sequential circuits is described. The two power-gating switches are inserted between the single-phase power-clock and virtual power-clocks to detach power-gated sequential logic blocks and to refresh the storage value of power-gating adiabatic flip-flops during idle periods. A practical sequential system realized with the proposed single-phase power-gating adiabatic flip-flops is demonstrated. SPICE simulations show that energy loss of the single-phase adiabatic sequential circuits can be greatly reduced by shutting down adiabatic logic blocks during idle periods.

关键词： Flip-flops Clocks logic circuits MOSFETs Sequential circuits Energy loss cmos technology Circuit simulation cmos logic circuits Recycling

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Reduced Complementary Dynamic and Differential logic: A cmos logic Style for DPA-Resistant Secure IC Design

Reduced Complementary Dynamic and Differential Logic: A CMOS...

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International Conference on VLSI Design

作者： Srividhya Rammohan Vijay Sundaresan Ranga Vemuri Department of ECE. University of Cincinnati Cincinnati OH USA

ISBN: (纸本)9780769530833;0769530834

In recent years, Differential Power Analysis (DPA) attack has become a major threat to the security of embedded cryptographic ICs (secure ICs) like smart cards. DPA attack is a powerful side-channel attack. During a DPA attack, the attacker uses power consumption measurements from the secure IC and statistical techniques to correlate the power consumption information leaked with the secret key stored in the secure IC, thus retrieving the secret key, and effectively breaking the secure IC. In this paper, we present a Reduced Complementary Dynamic and Differential logic (RCDDL) style to design DPA-resistant, secure ICs. RCDDL style ensures that the power consumption of the secure IC remains invariant, and hence, uncorrelated to the input data (secret key). As opposed to existing DDL styles that complement every gate in the uncomplementary logic to generate the differential output, RCDDL style proposes reuse of gates, thus ensuring that a reduced number of gates in the uncomplementary logic are complemented to generate the differential output. Further, we present an analysis of how reduced complementation is achieved while maintaining the capacitance and switching requirements for power invariance. To evaluate the proposed logic style, we built a set of logic gates typically used to design secure ICs. Experiments on a set of circuits, designed using the set of RCDDL gates, show significant improvements in security strength, power consumption and area.

关键词： cmos logic circuits logic design cmos integrated circuits Energy consumption Information security Cryptography Smart cards Power measurement Information retrieval Capacitance

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A Highly Reliable logic NVM "eCFlash (Embedded cmos Flash)" Utilizing Differential Sense-Latch Cell with Charge-Trapping Storage

A Highly Reliable Logic NVM "eCFlash (Embedded CMOS Flash)" ...

引用

IEEE International Memory Workshop (IMW)

作者： T. Ogura M. Mihara Y. Kawajiri K. Kobayashi S. Shimizu S. Shukuri N. Ajika M. Nakashima GENUSION Inc. Amagasaki Hyogo Japan

ISBN: (纸本)9781424415465;1424415462

A new logic NVM "eCFlash (embedded cmos Flash)" has been developed without any additional process steps in a 0.25 um technology. In this architecture, a novel differential sense-latch cell with charge-trapping storage is adopted. This unique cell structure functions as a differential sense amplifier as well as a data latch, therefore mass data can be restored to each cell's latch simultaneously for static data output with high sensitivity and low power consumption. Furthermore the handling scheme of twice the breakdown voltage with novel charge pump circuit and high voltage driver is demonstrated. By utilizing these techniques, a highly reliable logic NVM is realized; 100 K cycling endurance and data retention of 20 years at 150C.

关键词： cmos logic circuits Latches cmos process cmos technology Differential amplifiers High power amplifiers Energy consumption Charge pumps Breakdown voltage Driver circuits

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