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检索条件"主题词=CMOS Logic Circuits"

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Innovative Power Gating for Leakage Reduction

Innovative Power Gating for Leakage Reduction

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.5

作者： Masud H. Chowdhury Juliana Gjanci Pervez Khaled Department of Electrical & Computer Engineering University of Illinois Chicago Chicago IL USA

Leakage has become one of the most dominant factors of power management and signal integrity of nanometer scale integrated circuits. Recently, power gating structures has proven to be effective in controlling leakage. In this paper an alternative dual-V_(th) reduced power gating structure is proposed for better reduction of leakage currents, especially for low-power, high-performance portable devices. The proposed technique maintains an intermediate power saving state as well as the conventional power cut-off state. The experimental results have demonstrated that the proposed technique can significantly reduce leakage current and associated power consumptions during the HOLD and CUT-OFF power saving modes.

关键词： Leakage current Threshold voltage cmos technology cmos logic circuits Energy consumption logic circuits Delay Gate leakage Network-on-a-chip Power engineering computing

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Low-Power Short-Channel Single-Ended Current-Steered cmos logic-Gate for Mixed-Signal Systems

Low-Power Short-Channel Single-Ended Current-Steered CMOS Lo...

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.7

作者： Ajay Taparia T.R. Viswanathan Department of Electrical Engineering University of Texas Dallas Richardson TX USA Electrical and Computer Engineering University of Texas Austin Austin TX USA

Low-power cmos logic circuits operated from a fixed supply voltage can result in uncontrolled conduction over process and temperature variation. Large current-pulses flowing during the logic transitions also cause power-supply noise. Current steered logic known as CSL can mitigate these problems. Here, a fixed bias-current is steered between two distinct paths during the transition between logic states. Constant supply-current eliminates switching noise on the power supply line. The current-biased circuit presented here operates like a normal cmos gate preserving many of its desirable properties. The key modification is that the output static-voltage of the gate is used to steer the bias current between two paths. During the transition the bias current is used for pulling-up the output node. During the pull-down phase a small local capacitance is charged to provide the current pulse needed for pull-up. The current source resistance in conjunction with the local decoupling capacitor acts as a bypass for the impulse current needed for quick pull-up. This new circuit operates over a wide range of bias currents and, the corresponding speeds vary proportionately. These current-steered cmos gates (CS-cmos) are specially targeted for use in low-power, wide dynamic range mixed-signal applications where supply noise must be minimized. Circuit operation and simulation results are presented.

关键词： cmos logic circuits Voltage Circuit noise cmos technology Temperature Power supplies logic devices Capacitors Capacitance Negative feedback

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Mitigation of cmos Device Variability in the Transmitter Amplitude Path using Digital RF Processing

Mitigation of CMOS Device Variability in the Transmitter Amp...

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.2

作者： Khurram Waheed Robert B. Staszewski Wireless RF-CMOS Radio Design Texas Instruments Inc. Dallas TX USA

Digital RF Processor (DRP~(TM))-based GSM/EDGE transmitter is built using dense and fast digital logic and comprises two converters that transform transmit modulation from digital to RF frequency/phase and amplitude analog domains. Using the concept of digital at the service of analog, DRP transmitters employ a number of estimation and compensation algorithms to provide robust performance in the presence of cmos device variability. This paper describes digital techniques to counter the random and systematic mismatches in the amplitude path of the small-signal DRP transmitter. Furthermore, the DRP-based small signal polar EDGE transmitter utilizes a non-linear digitally-controlled pre-power amplifier (DPA) with optimized power-added efficiency (PAE). The DPA is used for on-chip combination of the amplitude and phase modulation paths, which exhibit variable transfer characteristics due to process, voltage, temperature and aging. For stringent transmitter (TX) performance requirements, the DPA needs to be linearized in the dynamic TX operational environment. The techniques presented are employed in a commercial Texas Instruments single-chip GSM/EDGE radio realized in nanoscale cmos.

关键词： cmos process Radio frequency Radio transmitters GSM Phase modulation cmos logic circuits logic devices Analog-digital conversion Digital-to-frequency converters Amplitude modulation

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High-quality Circuit Synthesis for Modern Technologies

High-quality Circuit Synthesis for Modern Technologies

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Ninth International Symposium on Quality Electronic Design (ISQED 2008)

作者： Lech Jozwiak Artur Chojnacki Aleksander Slusarczyk Eindhovan University of Technology Netherlands PDF Solutions Inc.

Due to weaknesses in circuit synthesis methods used in today's CAD tools, the opportunities created by modern microelectronic technology cannot effectively be exploited. This paper considers the issues and requirements of circuit synthesis for the nano cmos technologies, and discusses our new circuit synthesis technology that satisfies these requirements. The new technology considerably differs from all other known synthesis methods and overcomes their main weaknesses. The experimental results demonstrate that it produces very fast, compact and low-power circuits. The new technology has however many more major advantages that are discussed in the paper.

关键词： Circuit synthesis cmos technology Integrated circuit interconnections Power system interconnection Network synthesis cmos logic circuits logic circuits Paper technology Microelectronics Scalability

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High Speed Single-Ended Pseudo Differential Current Sense Amplifier for SRAM Cell

High Speed Single-Ended Pseudo Differential Current Sense Am...

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.10

作者： Abhijit Sil Eswar Prasad Kolli Soumik Ghosh Magdy Bayoumi Center for Advanced Computer Studies University of Louisiana Lafayette Lafayette LA USA

With reducing feature sizes, SRAM stability has become a major concern for future technologies. This critical issue can be solved by using highly stable separate bit-line read SRAM cell, but access time improvement becomes critical, since differential sense amplifier cannot be used for single bit-line read operation. In this paper, a novel pseudo differential single ended current mode sense amplifier is proposed. We demonstrate that this design can deliver a performance similar to that of conventional current mode differential amplifier without using dual bit-line for read operation. The overall read operation delay of the proposed single-ended design is almost 60percent less than conventional single-ended design in 90nm cmos technology. The proposed design consumes 51.6percent less energy than conventional design counterpart.

关键词： Differential amplifiers Random access memory Operational amplifiers Voltage cmos logic circuits Stability Delay cmos technology Capacitance Microprocessors

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Area Oriented Pass-Transistor logic Synthesis Using Buffer Elimination and Layout Compaction

Area Oriented Pass-Transistor Logic Synthesis Using Buffer E...

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.6

作者： Shen-Fu Hsiao Ming-Yu Tsai Chia-Sheng Wen Department of Computer Science and Engineering National Sun Yat-sen University Kaohsiung Taiwan

This paper presents a cell-based AISC design flow where the traditional cmos cell library is replaced by pass-transistor logic (PTL) cell library. In particular, we develop an automatic PTL logic synthesizer to perform area-oriented synthesis by exploiting the characteristics of the PTL cell circuits. Two methods are used to reduce the area cost. The first method, called buffer elimination, for the pre-layout area minimization is to reduce the redundant inverters in the gate-level netlist during the logic mapping stage and results in an area saving of more than 50percent. The second method, called layout compaction, is to reduce the layout area in the physical level by considering the design rules imposed on the PTL cell circuits, and lead to an additional 30percent area saving.

关键词： Compaction cmos logic circuits Circuit synthesis Libraries logic design Automatic logic units logic circuits Synthesizers Costs Minimization

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A 25MHz All-cmos Reference Clock Generator for XO-Replacement in Serial Wire Interfaces

A 25MHz All-CMOS Reference Clock Generator for XO-Replacemen...

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.8

作者： M. S. McCorquodale S. M. Pernia S. Kubba G. Carichner J. D. O'Day E. Marsman J. Kuhn R. B. Brown Mobius Microsystems Inc. Design Center Detroit MI USA College of Engineering University of Utah Salt Lake City UT USA

A 25MHz all-cmos clock generator is demonstrated where measured performance makes it suitable for direct replacement of the reference crystal oscillator (XO) for serial wire interfaces. Fabricated in a 0.25(mu)m 1P5M logic cmos process, and with no external components, the developed clock generator dissipates 59.4mW while exhibiting +-152ppm frequency error over process, +-10percent variation in the power supply voltage and from -5-75 deg C. Nominal period jitter and power-on start-up latency are 3.93ps_(rms) and 268(mu)s respectively.

关键词： Clocks Wire Oscillators cmos logic circuits cmos process Power generation Frequency Power supplies Voltage Jitter

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Circuit Techniques for Ultra-Low Power Subthreshold SRAMs

Circuit Techniques for Ultra-Low Power Subthreshold SRAMs

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.8

作者： Tae-Hyoung Kim Jason Liu John Keane Chris H. Kim Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA

Subthreshold operation has become an important area in applications where minimal power consumption and energy efficiency are the critical constraints. In particular, ultra-low power SRAM designs are critical for implementing such applications due to the large portion of the systems that they account for. However, sub-threshold SRAMs have many design issues such as cell stability, readability, and writability. In this paper, we give an overview of sub-threshold SRAM design issues and discuss several circuit techniques. We will focus on SRAM cell stability during read and write operation, improved writability, and read port circuits for the design of an ultra-low power sub-threshold SRAMs.

关键词： Random access memory Circuit stability Energy consumption Voltage Degradation Application software cmos logic circuits Noise robustness Stability criteria Energy efficiency

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A Full-custom Design of AES SubByte Module with Signal Independent Power Consumption

A Full-custom Design of AES SubByte Module with Signal Indep...

引用

2008 IEEE International Symposium on circuits and Systems (ISCAS 2008), vol.10

作者： Liang Li Jun Han Xiaoyang Zeng Jia Zhao State-Key Lab of ASIC and System Fudan University Shanghai China

A full-custom design of AES SubByte module based on Sense Amplifier Based logic is proposed in this paper. Power consumption of this design is independent of both value and sequence of data. Therefore this design is resistant to power analysis attack. This design is implemented using SMIC 0.18um cmos technology. Simulation results show that it can work at the frequency of 83.3MHz, and its total area is about 0.85mm~(2). This design is suitable for application in the hardware implementation of symmetric-key cryptographic devices that have high security demand.

关键词： Signal design Energy consumption cmos logic circuits logic design Frequency Cryptography Pipelines Information security Capacitance Power amplifiers

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Feedback-Switch logic (FSL): A High-Speed Low-Power Differential Dynamic-Like Static cmos Circuit Family

Feedback-Switch Logic (FSL): A High-Speed Low-Power Differen...

引用

Ninth International Symposium on Quality Electronic Design (ISQED 2008)

作者： Charbel J. Akl Magdy A. Bayoumi The Center for Advanced Computer Studies (CACS) University of Louisiana Lafayette LA USA

We present a new dynamic-like static circuit family called Feedback-Switch logic (FSL) that is suitable for high-speed low-power applications. FSL is a derivative of Cascode Voltage Switch logic (CVSL) family. However, it does not suffer from the contention problems of clockless CVSL, and it consumes much less power than clocked CVSL (dual-rail domino). FSL gates offer fast switching, reduced capacitance, and input-switching dependent activity factor without the need of clock connection. An 18-bit majority voting circuit is simulated in a 90-nm technology, in order to compare static, clockless CVSL, dual-rail domino and FSL. Simulation results show that FSL reduces delay by 21% compared to static logic, and offers at least 46% power reduction compared to dynamic dual-rail domino logic with two-phase skew-tolerant clocking.

关键词： cmos logic circuits Feedback circuits Clocks Switches Circuit simulation logic circuits Voltage Capacitance Voting Delay

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