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Finding hidden oscillations in the operation of nonlinear electronic circuits

ELECTRONICS LETTERS 2016年第12期52卷 1010-+页

作者： Rocha, R. Medrano-T, R. O. Univ Fed Ouro Preto UFOP EM DECAT Sch Mines Dept Engn Control & Automat BR-35400000 Ouro Preto MG Brazil Univ Fed Sao Paulo UNIFESP DCET Dept Exact Sci & Earth BR-09972270 Diadema SP Brazil

Several dynamic behaviours can simultaneously coexist in the operation of a nonlinear electronic circuit. However, some of these dynamics are difficult to be observed due to their sensibility to initial conditions. The use of describing functions to determine the coexistence of multiple dynamics in the operation of an electronic circuit with nonlinear feedback is proposed.

关键词： prescalers clocks flip-flops cmos logic circuits voltage 1 2 V size 180 nm power 0 81 mW frequency 4 2 GHz power consumption cmos dual-modulus operation divider pass transistor logic circuit true single-phase clock D flip-flop triple-modulus prescaler

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Ultra-Compact sub-10nm logic circuits Based on Ambipolar SB-FinFETs

Ultra-Compact sub-10nm Logic Circuits Based on Ambipolar SB-...

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IEEE Pulsed Power Conference

作者： Talha Furkan Canan Savas Kaya Avinash Kodi Hao Xin Ahmed Louri School of Electrical Eng. & Computer Sci. Ohio University Department of Electrical and Computer Eng. University of Arizona Department of Electrical and Computer Eng. George Washington University

ISBN: (纸本)9781509063901

Novel ultra-compact sub-10nm XOR, NOR and NAND cmos logic circuits based on ambipolar characteristics of Schottky-Barrier (SB) FinFET devices and gate metal workfunction engineering are introduced. Use of SB source and drain contacts, high-k gate dielectrics and ultra-thin body bestows extreme short-channel immunity to the proposed FinFETs with ambipolar current-voltage characteristics. Thus, the main physical parameter left for practical device design and threshold control is the gate workfunction along with independent-gate drive, which is creatively used in this work to build a novel conjugate (n/p channel) cmos pass-gate transistor that can function as a two-transistor (2T) XOR gates as opposed to 4 transistor conventional pass-gates. In a similar fashion, gate workfunction engineering can be utilized to design unique ambipolar FinFETs with two independent gates and high thresholds to function as 2T NAND and NOR gates. Functionality of the proposed minimalist logic circuits are verified with Synopsys TCAD simulations, which indicate that optimized gate work-functions lead to cmos logic circuits as small as 5nm and supply voltage of 0.6V, with a power-delay product at 5 × 10~(-18) J level.

关键词： ambipolar cmos logic circuits gates logic circuits Fin field effect transistors Device Design supply voltage NAND exclusive OR DRIVES Automobile driving THIN BODIES

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Corrections to “MagCAD: A Tool for the Design of 3-D Magnetic circuits” [2017 65-73]

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IEEE Journal on Exploratory Solid-State Computational Devices and circuits 2017年第1期3卷 111-111页

作者： Fabrizio Riente Umberto Garlando Giovanna Turvani Marco Vacca Massimo Ruo Roch Mariagrazia Graziano Electronics and Telecommunications Department Politecnico di Torino Turin Italy

In the above-named work, Tables 2 – 5 in the results section report the performance of different logic circuits. Unfortunately, due to a mistake, the bounding box area reported for all circuits is higher than their actual value. Tables 2 – 5 in [1] are here reprinted with the correct area. Moreover, the bounding box area of the 4-bit RCA and the 32-bit RCA are 105.47 and $2191.77~\mu \text{m}^circuits$ , respectively. The authors regret their mistake.

关键词： Magnetoelectronics Design tools logic design cmos logic circuits Integrated circuit modeling

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Robust near-threshold inverter with improved performance for ultra-low power applications

Robust near-threshold inverter with improved performance for...

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IEEE International Symposium on circuits and Systems (ISCAS)

作者： Md Shazzad Hossain Ioannis Savidis Department of Electrical and Computer Engineering Drexel University Philadelphia PA

ISBN: (纸本)9781479953424

Near-threshold computing (NTC) is a promising technique for low power applications. In this paper, novel circuit techniques for near-threshold computing are developed for improved power, performance, and robustness to noise. Two separate differential signaling based circuits are proposed which outperform cmos and current-mode logic (CML) operating at near-threshold. The proposed circuits are described as dynamic current-mode logic (DCML) and latched DCML (LDCML). Characterization of the cmos, CML, and the proposed DCML logic families is performed for area, power, performance and noise immunity at both the nominal and near-threshold operating voltages. At a near-threshold voltage, the DCML logic family reduces the total power by 32% while improving the performance by 82% as compared to cmos logic. The use of DCML logic also reduces the total power consumption by 92% while improving the performance by 64% as compared to CML logic operating at near-threshold. In addition, the robustness of the proposed logic families to noise is analyzed. At near-threshold voltages, both the noise margins of LDCML is improved by more than 1.4x as compared to cmos logic.

关键词： power consumption cmos logic circuits current-mode logic flip-flops integrated circuit noise logic gates low-power electronics current-mode logic cmos logic circuits Integrated circuit noise low-power electronics flip-flops Power consumption logic gates Noise margins cmos logic power performance Formal logic Complementary Metal Oxide Semiconductor aggregate capacity circuit technique

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A Web-Based Method for Building and Simulating Standard Cell circuits-A Classroom Application

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COMPUTER APPLICATIONS IN ENGINEERING EDUCATION 2015年第2期23卷 304-313页

作者： Beg, Azam United Arab Emirates Univ Coll Informat Technol Al Ain U Arab Emirates

The characterization of standard cells (basic digital blocks) is an iterative and arduous process. Our web-based tool enables the students/users to quickly perform a large number of characterization experiments. The tool is useful for various courses on micro/nano-electronics and circuit design, and eliminates the need for costly CAD-software/hardware. (c) 2014 Wiley Periodicals, Inc. Comput Appl Eng Educ 23:304-313, 2015;View this article online at;DOI

关键词： cmos logic circuits standard cell characterization SPICE simulation engineering education web-based tool

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A 4th-order analog continuous-time filter designed using standard cells and automatic digital logic design tools

A 4th-order analog continuous-time filter designed using sta...

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International Symposium on circuits and Systems

作者： Scott M. Newton Peter R. Kinget Dept. of Electrical Engineering Columbia University New York USA

ISBN: (纸本)9781479953424

An inverter-transconductor-based continuous-time analog 4th-order low-pass Butterworth filter was described entirely in Verilog hardware description language (HDL) using only standard cells. The physical design was synthesized with automated digital logic place-and-route (APR) CAD tools. APR was achieved in less than a minute making for an enormous improvement compared to traditional manual analog chip layout. A test chip was fabricated in a 0.18um cmos technology and its performance was experimentally verified. The experimental results document excellent measured performance and a huge physical design timesaving thereby validating the proposed automated design methodology.

关键词： logic design cmos logic circuits continuous time filters hardware description languages continuous time filters Hardware design languages cmos logic circuits logic design Batteries design tools digital logic Butterworth filters test chip

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Implementation of efficient modular bypass multiplier logic in RSA cryptographic processor

Implementation of efficient modular bypass multiplier logic ...

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International Conference & Workshop on Electronics & Telecommunication Engineering (ICWET 2016)

作者： S. Nirmala R. Praveena Muthayammal Engineering College Rasipuram Tamil Nadu IN Sengunthar College of Engineering Tiruchengode Tamilnadu India

ISBN: (纸本)9781510837225

Data security is in high demand in day to day digital life, complex cryptographic structures need to be modified to address the need of security from smart phones to define computers. This work focuses on both speed and area concerning objective. Numerous control strategies are introduced in both Gate and cmos level, Multipliers are the basic design unit of a reconfigurable cryptographic processor. As cryptography structure majorly depends on multiplier and modular units, this paper utilizes the advantage of Bypass multiplier with modified modular multiplier logic with reduces area over ahead more than 8% and speed optimization to 25%.

关键词： cmos logic circuits public key cryptography

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An ultra-low-power variable-accuracy bit-serial FFT butterfly processing element for IoT sensors

An ultra-low-power variable-accuracy bit-serial FFT butterfl...

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IEEE Asia-Pacific Conference on circuits and Systems

作者： Yue Lu Tom J Kazmierski School of Electronics and Computer Engineering University of Southampton Southampton UK

ISBN: (纸本)9781509015719

A key challenge in the design of Internet-of-Things sensors, specifically those powered by energy harvesters, is to minimise the power consumption and realize energy-scalable operation to meet the requirements of the variable power source. This paper proposes an ultra-low power Decimation-in-Time (DIT) radix-2 butterfly arithmetic block for an FFT processor, designed using a bit-serial architecture and operating at a near-threshold voltage (0.6 V). The bit-precision of the design can be dynamically adjusted between 8 and 16 bits. The reduced precision processing can decrease operation clock cycles and energy consumption. The proposed design is demonstrated using IBM 130-nm cmos logic process and results show that at a 16kHz throughput frequency, the active power and energy consumption are only 315 nW and 31 pJ per butterfly respectively for 16-bit accuracy. This represents a saving of 61 % and 84 % respectively compared with an equivalent state-of-the-art parallel design. Furthermore, approximately a 46.2 % additional energy saving can be achieved if the bit precision is reduced to 8 bits.

关键词： microprocessor chips cmos logic circuits digital arithmetic fast Fourier transforms Internet of Things low-power electronics

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Design of ultra-low-leakage near-threshold dynamic circuits in nano cmos for IoT applications

Design of ultra-low-leakage near-threshold dynamic circuits ...

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IEEE Conference on Nanotechnology

作者： Bo-Hao Chen Pei-Yuan Chou Ya-Bei Fang Lee-Kee Yong Tay-Jyi Lin Jinn-Shyan Wang Dept. of EE CCU Taiwan MediaTek Taiwan

IoT edge devices demand ultra-low leakage for lowly duty-cycled applications. It is usually believed that the static near-threshold-voltage (near-Vt) cmos circuit is the only circuit style that is suitable for designing devices to achieve low power, low leakage, medium performance, and high robustness against PVT variations. In this work, we show that the dynamic circuit can be even better than the static circuit under the same performance requirement. First, through a design example, we obtain basic design guidelines for near-Vt dynamic circuits. Second, based on the obtained design guidelines, we demonstrate how to design a dynamic circuit with active and standby operation modes using a 32b ripple carry adder (RCA). All designs are based on 28 nm cmos technology. We also compare the active and leakage power consumptions of both types of circuits of the same performance. For an IoT application with a 0.02% duty cycle, the 32b dynamic RCA achieves a 35% energy reduction compared to the static counterpart.

关键词： nanoelectronics adders cmos logic circuits integrated circuit design logic design dynamic circuit cmos logic circuits logic design integrated circuit design adders Nanoelectronics Energy conservation

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Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells

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IET circuits DEVICES & SYSTEMS 2015年第3期9卷 204-212页

作者： Dokania, Vishesh Islam, Aminul Birla Inst Technol Dept Elect & Commun Engn Ranchi 835215 Jharkhand India

Modern digital circuits are facing aggressive technology and voltage scaling under emerging technology generations. This study proposes a circuit-level technique to mitigate the adverse effects of process, voltage and temperature (PVT) variations on the design metrics of full adder (FA) cells under such ultra-deep sub-micron technology nodes. The proposed FA cells exhibit improved variability because of the use of inverting low voltage Schmitt trigger sub-circuits incorporated in the designs in place of inverters. The proposed circuits have been designed to operate in the near-threshold region, which offers a trade-off between performance and power consumption. The comparative analysis based on Monte Carlo simulations in a SPICE environment, using the 16-nm complementary metal-oxide semiconductor predictive technology model, demonstrates that the proposed technique is capable of mitigating the impact of PVT variations on major design metrics such as power, delay and power-delay product in FA cells. This improvement is achieved at the expense of two extra transistors for every replaced inverter in the FA cell.

关键词： voltage scaling logic gates complementary metal-oxide semiconductor full adder cells full adder cell design metric FA cells power-delay product aggressive technology adders circuit-level design technique trigger circuits PVT variations complementary metal-oxide semiconductor predictive technology model Monte Carlo simulations SPICE environment ultra-deep sub-micron technology nodes near-threshold region logic design inverting low voltage Schmitt trigger sub-circuits size 16 nm process voltage and temperature variation impact mitigation digital circuits power consumption cmos logic circuits

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