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54th IEEE International Midwest Symposium on circuits and Systems (MWSCAS)

作者： Ou, Jack Sonoma State Univ Dept Engn Sci Rohnert Pk CA 94928 USA

ISBN: (纸本)9781612848570

This paper proposes a technique to obtain thermal noise coefficient (gamma) and corner frequency (f(co)) from simulation. Once determined, gamma and f(co) can be integrated into the g(m)/I(D) design flow to simplify cmos analog circuit design. A folded cascode operational transconductance amplifier (OTA) is designed to provide a point of comparison. A 10% error in input noise and a 25% error in output noise show that gamma and f(co) can indeed be integrated into the g(m)/I(D) design flow.

关键词： analog circuits cmos analog circuits cmos analogue integrated circuits corner frequency input noise error integrated circuit noise noise analysis output noise output noise error

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A new cmos grounded positive capacitance-multiplier and an up-to-date bibliography on capacitance multipliers

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2025年 190卷

作者： Senani, Raj Singh, Abdhesh Kumar Rai, Manish Netaji Subhas Univ Technol Dept Elect & Commun Engn Sect 3 New Delhi 110078 India Netaji Subhas Univ Technol Dept Elect & Commun Engn East Campus New Delhi 110031 India

The capacitance multiplier circuits using a variety of analog building blocks have currently been receiving prominent attention in the technical literature. This paper presents a classical but unexplored method of synthesising capacitance multiplier and a new grounded positive capacitance multiplier circuit derived by following this approach which employs thirty-two MOSFETs (all operating in saturation) and provides an electronically- controllable capacitance multiplication factor while employing a single grounded capacitor and without using any passive resistors, all of which are desirable features from IC implementation viewpoint. The circuit compares well with the other cmos-compatible capacitance multipliers known in the earlier literature. The workability of the proposed circuit has been established through SPICE simulations based on 0.18 mu m cmos technology parameters. In the last, in view of the recent surge of interest on capacitance multipliers, an up-to-date bibliography on capacitance multiplier techniques and circuits, covering the period 1966-July 2024, has been provided for the benefit of the readers.

关键词： cmos capacitance multiplier Electronically-variable capacitance Impedance converters/inverters cmos analog circuits MOSFETs

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New electronically fine-tunable cmos floating resistor configuration and its application

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AEU-INTERNATIONAL JOURNAL OF ELECTRONICS AND COMMUNICATIONS 2025年 192卷

作者： Yadav, Harshmani Bansal, Urvashi Senani, Raj Netaji Subhas Univ Technol Dept Elect & Commun Engn Sect 3 New Delhi 110078 India

A new cmos circuit configuration has been presented which can realize electronically fine-tunable linear voltage-controlled positive as well negative floating resistors from the same configuration by interchanging some circuit connections. The circuit employing eighteen MOSFETs, all of which are operated in saturation region, and the realises a floating resistance value is independent of the threshold voltage (VTH) of the MOSFETs. The realised resistance has been found to vary from 71.26 k ohm to 35.73 k ohm for positive values and from -71.06 k Omega to -35.53 k Omega for negative values, when the control voltage is varied from 0.4 V to 0.8 V in both the cases. An application of the proposed circuit is demonstrated by using it in a new configuration of a first order current-mode universal filter based on unity gain current followers which is capable of realising low-pass, high-pass and all pass-all the three filters from the same configuration. The workability of the proposed voltage-controlled resistance (VCR) circuit in positive and negative both modes, as well that of the quoted application circuit, has been demonstrated through simulations using CADENCE SPICE tools and 0.18 mu m cmos technology parameters, at DC bias voltages of +/- 1.25 V.

关键词： Linear voltage-controlled resistor Floating resistor cmos analog circuits Active filters

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Programmable monolithic Gm-C band-pass filter:: design and experimental results

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analog INTEGRATED circuits AND SIGNAL PROCESSING 2008年第1期54卷 21-29页

作者： Lebel, Eric Assi, Ali Sawan, Mohamad Ecole Polytech Montreal Dept Elect Engn Polystim Neurotechnol Lab Montreal PQ Canada United Arab Emirates Univ Dept Elect Engn Al Ain U Arab Emirates

We propose in this paper a programmable band-pass filter based on an array of fully differential transconductance circuits that controls the filter parameters. The signal path does not contain any switch, and fine-tuning of the filter parameters is implemented using programmable capacitors. A digital building block is implemented in the proposed band-pass filter to tune its central frequency as well as its bandwidth. The filter circuit is based on a biquad topology, which is designed and implemented with cmos 0.18 mu m technology. Experimental results show a programming ability of the center frequency between 5.9 and 58 MHz, and the quality factor can be tuned from 0.36 to 10. These features are obtained for a total power consumption of less than 10.5 mW from a single 1.8 V power supply.

关键词： cmos analog circuits transconductance programmable band-pass filters continuous-time filters capacitor arrays digital tuning

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Design and comparison of very low-voltage cmos output stages

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IEEE TRANSACTIONS ON circuits AND SYSTEMS I-REGULAR PAPERS 2005年第8期52卷 1545-1556页

作者： Aloisi, W Giustolisi, G Palumbo, G Univ Catania Dipartimento Ingn Elettr Elettron & Sistemi I-95125 Catania Italy

This paper analyzes and compares cmos output stages for very low-voltage operational amplifiers. The analysis was carried out by taking into account output stage performance parameters which also affect the characteristics of the overall amplifier. In particular, three quality factors were defined to afford the designer a better understanding of the relationships between current dissipation, area consumption, bandwidth, and linearity. Exploiting these new parameters, four output stages were analyzed in detail and compared. Finally, comparison results were validated by simulations.

关键词： analog integrated circuits cmos analog circuits low-voltage operational amplifiers output stages

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DC-DC converter for fuel-cells and portable devices in digital cmos technology

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analog INTEGRATED circuits AND SIGNAL PROCESSING 2008年第1期55卷 93-102页

作者： Boni, Andrea Carboni, Alessandro Facen, Alessio Univ Parma Dip Ingn Informaz I-43100 Parma Italy Silis Srl I-43100 Parma Italy

The manuscript discusses the design of an integrated DC-DC power converter in a digital 0.18 mu m cmos technology for fuel cells and portable applications. By means of a combined boost and switched-capacitor architecture and design optimization a suitable efficiency has been achieved without resorting to special process options and with a limited number of passive external components. The achieved results enable the implementation of a power-converter system for fuel-cell featuring low-cost and small size, as required by the market of portable devices.

关键词： DC-DC converters cmos analog circuits fuel-cells

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A 1-V 5-GHz cmos multiple magnetic feedback receiver front-end

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 2008年第6期56卷 1338-1348页

作者： Vitzilaios, Georgios Papananos, Yannis Theodoratos, Gerasimos Natl Tech Univ Athens Dept Elect & Elect Engn GR-15773 Athens Greece

In this paper, a receiver front-end module operating at 5 GHz and suitable for low-voltage operation is presented. The design consists of a single amplifying transistor low-noise amplifier topology that utilizes multiple magnetic feedback in order to simultaneously achieve high gain and high reverse isolation. In addition, a mixer topology for. optimum performance regarding gain, noise, and linearity under low-voltage operation is presented. The design has been fabricated in IBM's 0.13-mu m cmos technology, and the measured performance indicates a receiver conversion gain of 22.3 dB, a noise figure of 2.64 dB, and a third-order input intercept point of +0.1 dBm.

关键词： cmos analog circuits linearization techniques low-noise amplifier (LNA) mixer design receiver topology

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A 1.5-V 75-dB dynamic range third-order G_m-C filter integrated in a 0.18-μm standard digital cmos process

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IEEE JOURNAL OF SOLID-STATE circuits 2003年第7期38卷 1189-1197页

作者： Yodprasit, U Enz, CC Ecole Polytech Fed Lausanne Swiss Fed Inst Technol Elect Lab CH-1015 Lausanne Switzerland CSEM CH-2007 Neuchatel Switzerland

A design methodology of a cmos linear transconductor for low-voltage and low-power filters is proposed in this paper. it is applied to the analog baseband filter used in a transceiver designed for wireless sensor networks. The transconductor linearization scheme is based on regulating the drain voltage of triode-biased input transistors through an active-cascode loop. A third-order Butterworth low-pass filter implemented with this transconductor is integrated in a 0.18-mum standard digital cmos process. The filter can operate down to 1.2-V supply voltage with a cutoff frequency ranging from 15 to 85 kHz. The 1% total harmonic distortion dynamic range measured at 1.5 V for 20-kHz input signal and 50-kHz cutoff frequency is 75 dB, while dissipating 240 muW.

关键词： cmos analog circuits continuous-time filters G(m)-C filters low-power/low-voltage filters triode transconductors

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A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuits AND SYSTEMS 1997年第4期16卷 343-352页

作者： Chen, MJ Ho, JS NATL CHIAO TUNG UNIV INST ELECT HSINCHU 300 TAIWAN

In this paper we introduce a new subthreshold conduction CAD model for simulation of VLSI subthreshold cmos analog circuits and systems, This model explicitly formulates the back-gate bias effect and preserves the original advantages of the existing four-parameter model while reducing the fitting parameter number down to three, A transparent relationship between the fitting parameters and the process parameters has been derived, and its correlation with a recently widely used CAD model as well as with a well-known two-parameter model has been established, Our extensive measurement work on n-channel MOSFET's has highlighted the potential of the model in handling the variations in the subthreshold I-V characteristics at different back-gate biases arising from process variations, The mismatch analysis has further been successfully performed with emphasis on the reverse back-gate bias effect. In summary, the proposed model can serve as a promising alternative in the area of VLSI subthreshold cmos analog circuit simulation.

关键词： back-gate bias CAD model cmos analog circuits mismatch subthreshold process variation

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New high-Q discrete-time LC bandpass filter design with center frequency broadband tuning

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analog INTEGRATED circuits AND SIGNAL PROCESSING 2006年第2期48卷 151-157页

作者： El Oualkadi, A Paillot, JM Allam, R Univ Catholique Louvain Microelect Lab B-1348 Louvain Belgium Univ Poitiers LAII ESIP F-16021 Angouleme France

Discrete-time switched-capacitor filters have been in wide-spread used for a few years, for the realization of stable, accurate and high quality filters. This paper describes the design of a new 8-path pseudo switched-capacitor LC bandpass filter and its command circuit made up by a ring voltage controlled oscillator (VCO) with 'XOR' gates. The proposed architecture presents the possibility of tuning over a frequency broadband allowing to sweep different channels with a high quality factor. This circuit is intended to replace the surface acoustic wave (SAW) filters in broadband wireless applications. Experimental results carried out on a prototype show quality factors up to 200, and a tunable center frequency range of 300 MHz [250-550 MHz].

关键词： cmos analog circuits high-Q bandpass tunable filters switched-capacitor broadband

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