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Air-stable N-type printed carbon nanotube thin film transistors for cmos logic circuits

CARBON 2020年 163卷 145-153页

作者： Wei, Miaomiao Robin, Malo Portilla, Luis Ren, Yunfei Shao, Shuangshuang Bai, Lan Cao, Yu Pecunia, Vincenzo Cui, Zheng Zhao, Jianwen Univ Sci & Technol China Sch Nanotech & Nanobion SEID 398 Ruoshui RdSuzhou Ind Pk Suzhou 215123 Jiangsu Peoples R China Chinese Acad Sci Printable Elect Res Ctr Suzhou Inst Nanotech & Nanobion SEID 398 Ruoshui RdSuzhou Ind Pk Suzhou 215123 Jiangsu Peoples R China Soochow Univ Inst Funct Nano & Soft Mat FUNSOM Jiangsu Key Lab Carbon Based Funct Mat & Devices Joint Int Res Lab Carbon Based Funct Mat & Device 199 Renai Rd Suzhou 215123 Jiangsu Peoples R China Chinese Acad Sci Technol & Engn Ctr Space Utilizat Key Lab Space Utilizat 9 Deng Zhuang South Rd Beijing 100094 Peoples R China

The lack of long-term air-stable and solution-processed n-doping methods for printed single-walled carbon nanotube (SWCNT) thin film transistors (TFTs) limits their integrations into printed complementary metal-oxide-semiconductor (cmos) circuits. In this paper, a new chemically modified epoxy amine ink was developed as the chemical dopant and encapsulant to enable the uniform n-type SWCNT-TFTs with long-term air stability (6 months). The epoxy amine inks were dropped onto the printed p-type TFT device channels in a single-step solution process. As a result, printed top-contact n-type SWCNT-TFTs were obtained with well-balanced electrical chararcteristics comparable to their p-type counterparts. The matched p-type and n-type SWCNT-TFTs were thus integrated into the printed cmos inverters and NAND gates, which have both achieved proper logic operation at supply voltages below 1 V. In particular, the cmos inverters could operate with VDD down to 0.3V with associated peak power consumption of 0.06 mu W, showing full rail-to-rail output swings with voltage gains up to 22, trip voltages of -V-DD/2, and maximum noise margin of 0.42 Vat V-DD = 1.1 V (-76.4% of V-DD/2). Furthermore, the static characteristics of cmos inverters could be maintained for 3 months with negligible changes, proving the feasibility of this long-term air-stable n-doping method. (C) 2020 Elsevier Ltd. All rights reserved.

关键词： Semiconducting single-walled carbon nanotubes (sc-SWCNTs) Printed thin film transistors (TFTs) N-doped Epoxy resin Air stability cmos logic circuits

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HOT-CARRIER-RELIABILITY DESIGN GUIDELINES FOR cmos logic-circuits

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IEEE JOURNAL OF SOLID-STATE circuits 1994年第3期29卷 253-262页

作者： QUADER, KN MINAMI, ER HUANG, WJ KO, PK HU, CM Department of Electrical Engineering and Computer Science University of California Berkeley CA USA University of California Berkeley Berkeley CA US Dept. of Electr. Eng. & Comput. Sci. California Univ. Berkeley CA USA

Long-term ring-oscillator hot-carrier degradation data and simulation results are compared to demonstrate that a circuit reliability simulator BERT can predict cmos digital circuit speed degradation from transistor dc stress data. We present generalized hot-carrier-reliability design rules that translate device-level degradation rate to cmos circuit lifetime. The design rules, which consist of lifetime and speed degradation factors, can roughly predict cmos circuit degradation during the initial design, and can help reliability engineers to quickly estimate the overall product hot-carrier reliability. The NMOSFET and PMOSFET lifetime factors were found to obey 4/ft(rise) and 10/ft(fill) respectively. Typically, the NMOSFET and PMOSFET speed degradation factors are 1/4 and 1/2, respectively, with saturation region drain current as the monitor, while for a 100 MHz operating frequency and for an input rise time of 0.35 ns, the NMOSFET and PMOSFET time factors are 120 and 300, respectively.

关键词： Hot carriers Guidelines cmos logic circuits Degradation MOSFET circuits Predictive models Circuit simulation Bit error rate cmos digital integrated circuits Digital circuits

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Optimum transistor sizing of cmos logic circuits using logical effort theory and evolutionary algorithms

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INTEGRATION-THE VLSI JOURNAL 2018年 60卷 25-38页

作者： Singh, Kunwar Jain, Aman Mittal, Aviral Yadav, Vinay Singh, Atul Anshuman Jain, Anmoll Kumar Gupta, Maneesha Netaji Subhas Inst Technol New Delhi India

Most existing methodologies use either logical Effort (LE) theory or stand-alone optimization algorithms for automated transistor sizing of cmos logic circuits. LE theory optimizes a logic circuit only with respect to speed while it completely ignores power and area. Whereas heuristic algorithms when used as a stand-alone approach for optimization lead to huge computational effort since there is no predefined technique to apply constraints on transistor sizes in order to limit the design space for target specifications. The problem has been resolved in this paper by utilizing delay sensitivity factor based on LE theory proposed by Alioto et. al. [1] for estimating the highest operating speed of a logic circuit and determining the upper bound on the size of transistors. Recently proposed heuristic algorithms viz. Interior Search Algorithm (ISA) [2] and Gravitational Search Algorithm (GSA) [3] have been utilized further to converge towards minimum power-delay-area product (PDAP). Simulation results for various test circuits indicate upto 35.1% and 63.8% improvement in power-delay product (PDP) and PDAP respectively in 130 nm/1.2 V TSMC cmos technology. PVT analysis and Monte Carlo simulations have been used to further validate the effectiveness of the proposed methodology.

关键词： Digital VLSI cmos logic circuits Optimization logical effort theory Heuristic algorithms Power-delay-area product

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OPTIMIZATION OF HIGH-SPEED cmos logic-circuits WITH ANALYTICAL MODELS FOR SIGNAL DELAY, CHIP AREA, AND DYNAMIC POWER DISSIPATION

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuits AND SYSTEMS 1990年第3期9卷 236-247页

作者： HOPPE, B NEUENDORF, G SCHMITTLANDSIEDEL, D SPECKS, W SIEMENS AG DEPT CORP RES & DEVMICROELECTR LABW-8000 MUNICH 83GERMANY RHEIN WESTFAL TH AACHEN INST THEORET ELECTRW-4100 AACHENGERMANY

Signal delay, chip area, and power dissipation are conflicting criteria for designing high-performance VLSI MOS circuits. Global optimization of transistor sizes in digital cmos logic circuits with the design tool multiobjective gate-level optimization (MOGLO) is described. Analytical models for the design objectives are presented, and algorithms are discussed. Different techniques were combined to solve the circuit optimization problem with low computational costs. Precise gate-level delay models guarantee meaningful results, especially for high-speed logic circuits.< >

关键词： cmos logic circuits Circuit analysis Delay Design optimization Power dissipation Signal design Very large scale integration Analytical models Algorithm design and analysis Circuit optimization

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Noise-tolerance improvement in dynamic cmos logic circuits

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IEE PROCEEDINGS-circuits DEVICES AND SYSTEMS 2006年第6期153卷 565-573页

作者： Mendoza-Hernandez, F. Linares-Aranda, M. Champac, V. Univ Sonora Dept Invest Fis Hermosillo Sonora Mexico Natl Inst Astrophys Opt & Elect INAOE Dept Elect Engn Puebla 72000 Mexico

Dynamic cmos logic styles are widely used in high-performance systems due mainly to their speed. However they have lower noise-tolerance than their static cmos counterparts. To overcome this disadvantage a new noise-tolerant circuit technique, suitable for precharge-evaluate dynamic circuits, is presented. The technique is suitable for TSPC and domino gates. Comparisons with previously reported noise-tolerant dynamic circuit techniques are presented. Simulation results on TSPC and domino gates show that the proposed technique improves the noise tolerance of conventional dynamic gates with reduced performance overhead. The feasibility of this new technique is demonstrated by means of a pipelined 0.35 mu m cmos carry look-ahead full adder. Experimental results show an increased noise tolerance of up to three times over standard cmos logic.

关键词： circuit noise TSPC fault tolerance dynamic cmos logic circuits pipelined cmos carry look-ahead full adder precharge-evaluate dynamic circuits multiplying circuits domino gates noise-tolerant circuit technique cmos logic circuits

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TESTING OF ZIPPER cmos logic-circuits

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IEEE JOURNAL OF SOLID-STATE circuits 1990年第3期25卷 877-880页

作者： TONG, Q JHA, NK Department of Electrical Engineering Princeton University Princeton NJ USA

Zipper cmos is a dynamic cmos circuit technique which also provides protection against instability and charge-sharing problems; this is achieved by using a special driver circuit. A method for testing of zipper cmos circuits is presented. The testing is done with the help of a single stuck-at-fault test set derived from the gate-level model of the circuit in which the vectors have to be properly arranged and sometimes also repeated. This test set detects not just all detectable stuck-at faults but stuck-open and stuck-on faults as well. Very few stuck-open faults require two-pattern tests, and very few stuck-on faults need current monitoring. Thus, zipper cmos circuits in particular and dynamic cmos circuits in general enjoy a huge testability advantage over static cmos circuits. Faults in the driver circuit are also considered.< >

关键词： Circuit testing logic testing cmos logic circuits Circuit faults Driver circuits Electrical fault detection Fault detection cmos technology Protection Semiconductor device modeling

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Statistical power estimation of cmos logic circuits with variable errors

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ELECTRONICS LETTERS 1998年第11期34卷 1054-1056页

作者： Park, YH Park, ES Elect & Telecommun Res Inst Taejon 305606 South Korea Hanyang Univ Dept Elect Engn Kyunggido 425791 South Korea

A statistical power estimation method is proposed where estimation time and accuracy can be balanced by assigning smaller (higher) errors to the nodes with higher (lower) power dissipation. To determine the errors, a quadratic programming based problem is formulated. Experimental results show a drastic reduction in the number of simulation patterns. compared to previous methods.

关键词： quadratic programming based problem Interpolation and function approximation (numerical analysis) error analysis estimation time Optimisation power dissipation cmos logic circuits cmos integrated circuits estimation theory Statistics logic circuits logic and switching circuits estimation accuracy Computer-aided circuit analysis and design circuit analysis computing quadratic programming Other topics in statistics Electronic engineering computing iterative methods Optimisation techniques variable errors statistical power estimation Numerical analysis Error analysis in numerical methods statistical analysis

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CALCULATION OF THE SOFT ERROR RATE OF SUBMICRON cmos logic-circuits

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IEEE JOURNAL OF SOLID-STATE circuits 1995年第7期30卷 830-834页

作者： JUHNKE, T KLAR, H Institute of Microelectronics Technical University Berlin Berlin Germany

A method to calculate the soft error rate (SER) of cmos logic circuits with dynamic pipeline registers is described, This methods takes into account charge collection by drift and diffusion, The method is verified by comparison of calculated SER's to measurement results, Using this method, the SER of a highly pipelined multiplier is calculated as a function of supply voltage for a 0.6 mu m, 0.3 mu m, and 0.12 mu m technology, respectively, It has been found that the SER of such highly pipelined submicron cmos circuits may become too high so that countermeasures have to be taken, Since the SER greatly increases with decreasing supply voltage, low-power/low-voltage circuits may show more than eight times the SER for half the normal supply voltage as compared to conventional designs.

关键词： Error analysis cmos logic circuits Registers Pipelines Voltage logic circuits Geometry Circuit simulation MOS devices cmos technology

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Hybrid Spintronics/cmos logic circuits Using All-Optical-Enabled Magnetic Tunnel Junction

IEEE OPEN JOURNAL OF NANOTECHNOLOGY

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IEEE OPEN JOURNAL OF NANOTECHNOLOGY 2022年 3卷 85-93页

作者： Dikshit, Surya Narain Nisar, Arshid Dhull, Seema Bindal, Namita Kaushik, Brajesh Kumar Indian Inst Technol Roorkee Dept Elect & Commun Engn Roorkee 247667 Uttar Pradesh India

Spintronics is one of the emerging fields for next-generation low power, high endurance, non-volatile, and area efficient memory technology. Spin torque transfer (STT), spin orbit torque (SOT), and electric field assisted switching mechanisms have been used to switch magnetization in various spintronic devices. However, their operation speed is fundamentally limited by the spin precession time that typically ranges in 10-400 ps. Such a time constraint severely limits the possible operation of these devices in high-speed systems. Optical switching using ultrashort laser pulses, on the other hand, is able to achieve sub-picosecond switching operation in magnetic tunnel junctions (MTJs). In this paper, all optically switched (AOS) MTJ has been used to design high speed and low power hybrid MTJ/cmos based logic circuits such as AND/NAND, XOR/XNOR, and full adder. Owing to the ultra-fast switching operation of AOS-MTJ, the circuit level results show that the energy and speed of AOS-MTJ based logic circuits are improved by 85% and 97%, respectively, when compared to STT based circuits. In comparison to SOT based designs, the proposed logic circuits show 10% and 91% improvement in energy efficiency and speed, respectively.

关键词： Magnetic tunneling Optical switches Magnetization Vertical cavity surface emitting lasers logic circuits Lattices Integrated circuit modeling All-optical-switching magnetic tunnel junction MTJ cmos logic circuits spintronics

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DESIGN OF TESTABLE cmos logic-circuits UNDER ARBITRARY DELAYS

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IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED circuits AND SYSTEMS 1985年第3期4卷 264-269页

作者： JHA, NK ABRAHAM, JA Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana IL USA

The sequential behavior of cmos logic circuits in the presence of stuck-open faults requires that an initialization input followed by a test input be applied to detect such a fault. However, a test set based on the assumption that delays through all gates and interconnections are zero, can be invalidated in the presence of arbitrary delays in the circuit. In this paper, we will present a necessary and sufficient condition for the existence of a test set, which cannot be invalidated under arbitrary delays, for an AND-OR or OR-AND cmos realization for any given function. We will also introduce a Hybrid cmos realization which, for any given function, is guaranteed to have a valid test set under arbitrary delays.

关键词： Circuit testing logic testing cmos logic circuits Delay Circuit faults Sequential analysis Electrical fault detection Fault detection Integrated circuit interconnections Sufficient conditions

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