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检索条件"主题词=CORDIC Algorithm"

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A VLSI Implementation of Double Precision Floating-Point Logarithmic Function 4

A VLSI Implementation of Double Precision Floating-Point Log...

引用

4th IEEE International Conference on Signal and Image Processing (ICSIP)

作者： Hao, Liu Wang Ming-Jiang Chen Mo-Ran Ming, Liu Harbin Inst Technol Fac Elect & Informat Engn HIT Campus Univ Town Shenzhen Shenzhen Peoples R China Shenzhen Inst Informat Technol Sino German Sch Shenzhen Peoples R China

ISBN: (纸本)9781728136608

Logarithmic operations have a wide range of applications in the multimedia field, such as speech recognition, computer vision. Double-precision floating-point operations are widely used in scientific computing, so the development of high-performance floating-point logarithmic computing units has become one of the hot research topics. Based on the cordic (Coordinate Rotation Digital Computer) algorithm, this topic improves its operation cycle and demonstrates and implements the hardware design of the 64-bit floating-point logarithmic unit. It has the characteristics of a short cycle and high precision and meets the requirements of IEEE754. The hardware architecture is described in the Verilog language and simulated and integrated to derive its performance. With 100Hz clock and TSMC 65nm technology, the total area is about 0.2mm(2) , which needs only 16 clock cycles to calculate a double precision logarithmic function.

关键词： floating-point number logarithmic function cordic algorithm VLSI double precision

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Digital Fast Startup Procedure for Micro-machined Vibratory Gyroscopes Using Optimized Fuzzy Control Strategy 9

Digital Fast Startup Procedure for Micro-machined Vibratory ...

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9th IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS)

作者： Wang, Long Zhao, Qiancheng Nie, Minghao Liu, Dachuan Liu, Yuxian Yan, Junjie Yang, Zhenchuan Yan, Guizhen Peking Univ Inst Microelect Natl Key Lab Sci & Technol Micro Nano Fabricat Beijing 100817 Peoples R China

ISBN: (纸本)9781479947263

In this paper, we present an optimized digital fuzzy control strategy in order to realize fast startup of MEMS gyroscopes in various ambient temperatures. In the proposed procedure, the MEMS (Micro-Electro-Mechanical Systems) vibratory gyroscope is driven with a sinusoidal wave synthesizer of adjustable frequency based on cordic algorithm. The drive frequency is fixed on the resonant frequency of the gyroscope with a frequency controller. By deliberate design of startup frequency controller using fuzzy control strategy, the startup time is decreased effectively in different ambient temperatures verified with test results. A series of startup test is performed under ambient temperatures ranging from -30 to 60 degrees C, the tested startup time is improved from similar to 2.5s (tested with PID frequency controller) to similar to 100ms. What's more, this procedure has a higher SNR of 88dB.

关键词： MEMS gyroscope cordic algorithm fuzzy control closed-loop drive system FPGA

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Calculation Angle and Amplitude Spectrum of Interferogram with FPGA

Calculation Angle and Amplitude Spectrum of Interferogram wi...

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5th International Symposium on Photoelectronic Detection and Imaging (ISPDI) - Imaging Spectrometer Technologies and Applications

作者： Liu, Jiaqing Ding, Lei Chinese Acad Sci Lab Infrared Detect & Imaging Shanghai 200083 Peoples R China

ISBN: (纸本)9780819497796

Historically, computationally-intensive data processing for space-borne instruments has heavily relied on ground-based processing system. But with recent advances in FPGAs such as Xilinx Virtex-4 and Virtex-5 series devices that including PowerPC processors and DSP blocks thereby provding a flexible hardware and software co-design architecture to meet computationally-intensive data processing need, So it is able to shift more processing on-board;for high data active and passive instruments, such as interferometer, Implementations of on-board processing algorithms to perform lossless data reductions can dramatically reduce the data rates, therefore relaxing the downlink data bandwidth requirements. The interferograms are performs the inverse fourier transform on-board in order to decrease the transmission rate. In [Revercomb et al.] paper show that only use the modulus of the complx spectrum will lead to big calibration errors. So the amplitude and angle of the complex spectrum is need for radiometric cablibration, but there have a big challenge for on board obtained the amplitude and angle of the complex spectrum. In this paper, we introduce the cordic algorithm to slove it. The cordic algorithm is an iterative convergence algorithm that performs a rotation iteratively using a series of specific incremental rotation angles selected so that each iteration is performed by shift and add operation, which fit for FPGA implementation, and can be parallel in a chip to fullfill different latency and throughput. Implemention results with Xilinx FPGA are summarized.

关键词： on-board data processing Interferogram FPGA cordic algorithm phase correction

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Kinematics Calculation of Minimally Invasive Surgical Robot based on FPGA

Kinematics Calculation of Minimally Invasive Surgical Robot ...

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IEEE International Conference on Robotics and Biomimetics (ROBIO)

作者： Jiang, Ziyang Dai, Yu Zhang, Jianxun He, Su Nankai Univ Coll Comp & Control Engn Inst Robot & Automat Informat Syst Tianjin Peoples R China

ISBN: (纸本)9781538637425

In order to achieve high precision master-slave heterogeneous surgical robot, this paper addresses the needs of robot in motion control. The forward kinematics model of the master arm is established by D-H method and the inverse kinematics model of the salve arm is established by algebraic method. We construct the kinematics hardware model by using cordic algorithm based on FPGA technology, and realize the complex solution for kinematics from the manipulator model in the microsecond time. The experimental results show that the kinematic calculation results based on FPGA are consistent with the theoretical results of computer simulation. In addition, the scheme greatly improves the response speed of the master and slave arms, which lays the foundation for the synchronization of the robot arm movement.

关键词： Master-slave Heterogeneous Robot Kinematics Model cordic algorithm FPGA

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An Efficient Hardware Implementation of Gaussian Random Number Generator

An Efficient Hardware Implementation of Gaussian Random Numb...

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International Conference on NextGen Electronic Technologies-Silicon to Software (ICNETS2)

作者： Kasiviswanathan, N. Srivatsan, K. VIT Univ Sch Elect Engn Madras Tamil Nadu India

ISBN: (纸本)9781509059133

A pair of 32 bit Gaussian Random Numbers (GRaNs) is generated. Box Muller (BM) transformation is widely used for generation of high quality Gaussian Random Numbers in hardware. The BM transformation is a direct method to convert random numbers into a Gaussian random numbers. For the generation of uniform random number skip-ahead linear feedback shift register (SA-LFSR) is used which is given as input to BM transformation. cordic algorithm is used for the hardware design of BM transformation. The SA-LFSR does not suffer from correlations since they skip n number of bits at every sample

关键词： Random numbers Box Muller (BM) algorithm Skip-Ahead Linear Feedback Shift Register (SA-LFSR) cordic algorithm

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Serial and Parallel Implementation of cordic Architecture: A Comparative Approach

Serial and Parallel Implementation of CORDIC Architecture: A...

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Annual International Conference on Emerging Research Areas (AICERA) / International Conference on Microelectronics, Communication and Renewable Energy (ICMiCR)

作者： Abubeker, K. M. Backer, Sabana Varghese, Abey Mathew Amal Jyothi Coll Engg Dept ECE Kottayam Kerala India KMEA Coll Engg Kottayam Kerala India Vel Tech Multitech Engg Coll Avadi India

ISBN: (纸本)9781467351492;9781467351508

Many hardware efficient algorithms exist for hardware signal processing architecture. Among these algorithm there is a set of shift-add algorithms collectively known as cordic (Coordinate Rotation for Digital Computers) for computing a wide range of functions including certain trigonometric, hyperbolic, linear and logarithmic functions. The paper compares the serial and parallel implementations of cordic architecture [1] with respect to their speed and device utilization. Both the implementations were done in Verilog, simulated using Modelsim simulator and Implemented in Xilinx FPGA synthesis on Spartan-3. [3]. In Parallel structure of cordic algorithm, with 31 iterations plus a PRELOAD cycle, the algorithm will take 32 clock cycles to complete. At the theoretical maximum clock frequency of 56.507 MHz, the unit will take 17.697 ns to compute the final value. A truly complete general unit that is capable of operating in all three domains in both modes should be possible with only a little more hardware.

关键词： cordic algorithm Spartan-3 Xilinx FPGA Sine Cosine and Polar-Cartesian Transformation Complex PLDs CLBs Rotating and Vectoring mode

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A Low-Area Based Costas Loop Implementation for BPSK Signals

A Low-Area Based Costas Loop Implementation for BPSK Signals

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International Conference on Electrical, Electronics, Communication, Computer, and Optimization Techniques (ICEECCOT)

作者： Sushma Venkataratnam Yellampalli, Siva UTL Technol Ltd Dept VLSI Design & Embedded Syst Bangalore 560022 Karnataka India

ISBN: (纸本)9781538623619

Modulation and Demodulation are the most critical blocks in a communication system. Demodulators used in coherent communication receivers not only get back the message signal, but also perform phase error detection and correction. Phase error detection and correction involves tuning or adjusting the phase of the reference signal to that of the carrier signal received. This is an iterative process. One of the popular techniques employed for phase error detection and correction is the Costas Loop. There has been research about Numerically Controlled Oscillators (NCO) based on cordic algorithm being used in a Costas Loop [1]. The other simple yet memory expensive alternative to the cordic algorithm is to use a Look-Up Table (LUT) based technique. This paper tries to model a Costas Loop based on each of the methods separately and then compare the results. There has been notable work involving the use of symmetric FIR filters in a Costas Loop [2] which saves on memory. However there has been no attempt to compare the results of folded filter (uses one half of the filter coefficients only) architecture versus that obtained from unfolded filter (uses the entire coefficient sequence) architecture implementations. This paper compares the results obtained from folded filter implementation versus that obtained from unfolded filter implementation. The system was simulated using MATLAB and Simulink. The Verilog implementation was programmed on Spartan 3e FPGA board.

关键词： Costas Loop LUT based NCO cordic algorithm Symmetric FIR filter Folded and unfolded filters MATLAB and Simulink Spartan 3e FPGA

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An FPGA Implementation of Singular Value Decomposition 27

An FPGA Implementation of Singular Value Decomposition

引用

27th Iranian Conference on Electrical Engineering (ICEE)

作者： Shiri, Aidin Khosroshahi, Ghader Karimian Tabriz Univ Fac Elect & Comp Engn Tabriz Iran

ISBN: (纸本)9781728115085

In linear algebra, Singular Value Decomposition (SVD) refers to factorization process of real or complex matrices that has many applications in engineering, including signal processing, image processing, robotics, bioinformatics, and so forth. Calculating SVD of a matrix by different algorithms always has been a challenge for engineers due to its complex and time-consuming computation process, so that in many cases its application was limited to non-real time offline designs. In this paper, we surveyed the algorithms for calculating SVD, and implemented a customized hardware structure according to the Jacobi algorithm on the FPGA for real-time computation of SVD of arbitrary matrices. Jacobi algorithm, is selected for implementation because of its high parallel processing potential. cyclic method for selecting four Respective elements of the matrix, and a new method for determining the number of sweeps without the time-consuming norm calculation process, along with engaging cordic algorithm for calculating basic trigonometric functions resulted in improvement regarding hardware compared to previous works.

关键词： Singular Value Decomposition FPGA cordic algorithm Hardware Implementation

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Digital Closed-loop Driver Design of Micromechanical Gyroscopes Based on Coordinated Rotation Digital Computer algorithm

Digital Closed-loop Driver Design of Micromechanical Gyrosco...

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8th Annual IEEE International Conference on Nano/Micro Engineered and Molecular Systems (NEMS)

作者： Liu, Yuxian He, Chunhua Liu, Dachuan Yang, Zhenchuan Yan, Guizhen Peking Univ Inst Microelect Natl Key Lab Sci & Technol Micro Nano Fabricat Beijing 100871 Peoples R China

ISBN: (纸本)9781467363525;9781467363518

A novel digital closed-loop driver is presented for a micromechanical vibratory gyroscope in this paper. Coordinated rotation digital computer algorithm is applied to generate the sine and cosine signals for driving and demodulation processing. Meanwhile, automatic gain control and phase-locked loop are adopted to maintain a constant velocity of the drive mode and guarantee the gyroscope working in the resonant mode. All the control methods are implemented in FPGA device. Experimental results demonstrate that the stability of the amplitude of the drive velocity is about 18ppm, which verifies the effectiveness and accuracy of the digital closed loop for the drive mode. The scale factor, nonlinearity and bias instability of the gyroscope with closed loop controlled sense mode are measured to be 18.5mV/deg/s, 0.088% and 19.4deg/h, respectively.

关键词： MEMS vibratory gyroscope Closed Loop LMS cordic algorithm

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Implementation of Frequency Domain Equalizer for Single Carrier Transmission

Implementation of Frequency Domain Equalizer for Single Carr...

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4th International Conference on Wireless Communications, Networking and Mobile Computing

作者： Gheorghiu, Valentin Kameda, Suguru Takagi, Tadashi Tsubouchi, Kazuo Adachi, Fumiyuki Research Institute of Electrical Communication Tohoku University Aoba-ku Sendai 980-8577 Katahira 2-1-1 Japan QUALCOMM Japan Inc. Dept. of Electrical and Communications Engineering Graduate School of Engineering Tohoku University Aramaki Aoba-ku Sendai 980-8579 6-6-05 Aza-Aoba Japan

ISBN: (纸本)9781424421077

Single-carrier (SC) transmission using frequency domain equalization (FDE) based on the minimum mean square error (MMSE) criterion is an efficient way to combat the effects of frequency selective fading. In this paper, we discuss several key aspects concerning the implementation of a frequency domain equalizer and propose a feasible design. One of the problems is the implementation of the division operator used to compute the equalization weights. The cordic algorithm was employed for this as it reduces the hardware overhead. The proposed design was implemented in a FPGA and the performance was evaluated through experimental data.

关键词： Single-carrier implementation FPGA cordic algorithm

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