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Improved VLSI architecture for triangular windowed sliding DFT based on cordic algorithm

IET CIRCUITS DEVICES & SYSTEMS 2019年第2期13卷 251-258页

作者： Kulshreshtha, Tanmai Dhar, Anindya Sundar Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

This study presents a very-large-scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (cordic) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high-throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB.

关键词： field programmable gate arrays discrete Fourier transforms VLSI hardware description languages digital arithmetic signal processing application specific integrated circuits VLSI architecture triangular windowed cordic algorithm very-large-scale integration architecture discrete Fourier COordinate rotation DIgital computer algorithm direct cascading SDFT modules odd bins correct outputs high-throughput rate computation proceeds final output generalised architecture (DFT) bins

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A scale factor correction scheme for the cordic algorithm

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IEEE TRANSACTIONS ON COMPUTERS 2008年第8期57卷 1148-1152页

作者： Sumanasena, M. G. Buddika Univ Moratuwa Dept Elect & Telecommun Engn Katubedda 10400 Moratuwa Sri Lanka

A method for the correction of the scale factor of the cordic algorithm is presented in this paper. The scheme requires some additional hardware for its implementation, but does not require changing the elementary rotation angles or the sequence of iterations of the standard cordic algorithm. Upper bounds for the quantization error when using the proposed method are derived. A word serial implementation of the algorithm is also given. For fixed-point arithmetic, the area and latency of the proposed implementation are compared with the standard cordic.

关键词： cordic algorithm computer arithmetics

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Design and Implementation of an Efficient Modified cordic algorithm 4

Design and Implementation of an Efficient Modified CORDIC Al...

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4th IEEE International Conference on Signal and Image Processing (ICSIP)

作者： Xue, Yuan Ma, Zhongsong Chinese Acad Sci Technol & Engn Ctr Space Utilizat Beijing Peoples R China Chinese Acad Sci Ctr Space Utilizat Key Lab Space Utilizat Technol & Engn Beijing 100094 Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781728136608

Coordinate Rotation Digital Computer (cordic) algorithm has greatly improved the efficiency of the hardware implementation of digital signal processing algorithms and other mathematical operations. While there exist quite a lot of redundant iterations in the Conventional cordic algorithm, this paper proposes a novel efficient modified cordic algorithm combining the Conventional cordic algorithm with the VSF cordic algorithm. And this new method has already been simulated and implemented on Cyclone IV FPGA. The results show that the number of iterations has been obviously reduced while the hardware resource consumption is also decreased to some extent.

关键词： cordic algorithm Sealing-Free FPGA

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Enhanced cordic algorithm using an Area Efficient Carry Select Adder

Enhanced CORDIC Algorithm using an Area Efficient Carry Sele...

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International Conference on Intelligent Sustainable Systems (ICISS)

作者： Inguva, Sharath Chandra Seventline, J. B. GITAM Univ GITAM Inst Technol Dept ECE Visakhapatnam AP India

ISBN: (纸本)9781538619599

In this paper, we have designed an efficient cordic algorithm, which is used to minimize the cordic rotation angle with the help of several rotations. The main idea of this new cordic algorithm is to use an area efficient carry select adder (CSLA), instead of using a normal adder. This adder can achieve fast arithmetic operation in various data processing techniques. Finally, the comparison of various parameters like area, power and delay are calculated and they are reduced in the proposed method when compared to the existing method.

关键词： cordic algorithm CSLA rotation friend angle

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IQ Imbalance Compensation based on cordic algorithm in VLC-OFDM System 10

IQ Imbalance Compensation based on Cordic Algorithm in VLC-O...

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10th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC)

作者： Liu, Peng Guo, Yarong Li, Yue Liu, Song North China Elect Power Univ Yangzhong Intelligent Elect Inst Beijing Peoples R China

ISBN: (数字)9781728109749

ISBN: (纸本)9781728109749

This study investigates the problem of in-phase and quadrature (IQ) imbalance in the visible light communication (VLC) system. The effectiveness of the blind compensation method based on coordinate rotation digital computer (cordic) algorithm against the IQ imbalance is discussed. We further verify the proposed compensation method with QPSK and 16QAM signals respectively, with simulated impairments caused by the light emitting diode (LED) nonlinearity. Additionally, the analysis of Monte Carlo simulation under the assumption of different signal-to-noise ratio (SNR) is showed where in some cases, the compensation intensity increases as the SNR increases.

关键词： LED nonlinearity IQ imbalance Visible light communication cordic algorithm

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Design and Implementation of cordic algorithm using Integrated Adder and Subtractor 6

Design and Implementation of CORDIC algorithm using Integrat...

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6th International Conference for Convergence in Technology (I2CT)

作者： Bhukya, Sreenivasu Inguva, Sharath Chandra Sreyas Inst Engn & Technol Dept ECE Hyderabad Telangana India St Peters Engn Coll Dept ECE Hyderabad Telangana India

ISBN: (纸本)9781728188768

cordic (Coordinate Rotation Digital Computer) has been designed and implemented in many variants in the past five decades where the different architectures of the algorithm were used in many diverse applications. cordic algorithm is a flexible shift and add algorithm having an important feature of reduced quantization errors in the case of higher word lengths when compared to other algorithms. The major issue with the algorithm is due to its linear rate convergence with the speed of iteration. Its overall performance is also affected due to repeated number of shift and adds operations and thereby leading to high power consumption. The main aim of this work is to use a new integrated adder and subtractor designed using reversible gates in the place of binary adders and subtractors used in the previous design. This improved cordic uses an architecture where the rotation angle is split into micro rotation angles, where these angle sets provides faster convergence by reducing the number of iterations. Overall performance of the proposed algorithm is implemented using variety of FPGA families like Virtex-4, Virtex-5 and Artix-7 devices with comparison to parameters like area, frequency and power consumed. It is compared with the Conventional cordic and LH cordic designs.

关键词： cordic algorithm Canonical signed-digit Hcub algorithm Integrated adder subtractor

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Low Latency VLSI Architecture for the Radix-4 cordic algorithm

Low Latency VLSI Architecture for the Radix-4 CORDIC Algorit...

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IEEE Region 10 Colloquium/3rd International Conference on Industrial and Information Systems

作者： Lakshmi, B. Dhar, A. S. Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781424428052

The current trend of hardware intensive signal processing is based on the cordic. Over the years many architectures have been proposed to address issues pertaining to throughput and latency. In this paper, we are proposing a pipelined architecture for the VLSI implementation of radix-4 cordic rotator with redundant arithmetic to achieve low latency compared to the available architectures.

关键词： cordic algorithm radix-4 rotation mode redundant arithmetic

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High Speed Architectural Implementation of cordic algorithm

High Speed Architectural Implementation of CORDIC Algorithm

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IEEE Region 10 Conference (TENCON 2008)

作者： Lakshmi, B. Dhar, A. S. Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781424424085

Advances in the VLSI technology have provided designers with significant impetus for porting algorithm into architecture. In this paper, we propose an architecture with low latency for the implementation of cordic algorithm in rotation mode suited for parallel and pipelined operation. In our proposed architecture, redundant radix-4 arithmetic is employed to reduce iteration delay and halve the number of iterations. The iteration delay is further reduced by predicting the directions of all microrotations without performing rotation.

关键词： cordic algorithm radix-4 rotation mode redundant arithmetic

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Restrained Latency Universal Modulator Outlay Adaptive cordic algorithm for Digital Communication

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JOURNAL OF APPLIED SECURITY RESEARCH 2021年第2期16卷 224-246页

作者： Suryakumari, K. Rao, N. Venkateswara Pragati Engn Coll Surampalem 533437 India Baptla Engn Coll Guntur Andhra Pradesh India

Digital communication plays a vital role in today's communication system in this electronic world. However, the applications of digital communication are limited due to the requirements of antenna with fully programmable circuits having modulators and de-modulators. It may also end with hardware complexities. In order to overcome such complexities, a universal modulator is designed with an efficient iterative method named as cordic algorithm in prior methods. Although, the cordic (Coordinate Rotation Digital Computer) algorithm works efficiently, it leads to computational as well as memory complexities. Additionally it creates a need for latency reduction strategy. Therefore, to compete with all these issues faced with the prior method, we proposed an amended cordic algorithm in universal modulator working with the principle of the harmonized Stone-Weierstrass theorem. In addition, the Newton-Raphson method and Remz algorithm are introduced here to reduce the memory complexity by doubling the number of iterations and to select the best carrier signal, respectively. Thus, our proposed work effectively unravels all the notorious issues caused with the conventional cordic algorithm and the proposed universal modulator is implemented in Xilinx.

关键词： cordic algorithm harmonized Stone-Weierstrass theorem Newton-Raphson method Remz algorithm universal modulator

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A direct digital frequency synthesizer based on cordic algorithm implemented with FPGA 5

A direct digital frequency synthesizer based on CORDIC algor...

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5th International Conference on ASIC

作者： Wang, Y Zhu, KJ Min, H Fudan Univ State Key Lab ASIC & Syst Shanghai 200433 Peoples R China

ISBN: (纸本)078037889X

A direct digital frequency synthesizer (DDFS) applied to digital modulation is presented, which can synthesize a 16-bit output sine and cosine wave with a spectrum density of-100dB at 50 MHz. The synthesizer covers a bandwidth from dc to 25 MHz in steps of 0.18 Hz with latency of 11 clock cycles. The structure is based on cordic algorithm. The whole digital system is implemented with FPGA.

关键词： direct digital frequency synthesizer (DDFS) field programmable gate array(FPGA) look-up-table ROM cordic algorithm

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