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19th Chinese Intelligent Systems Conference, CISC 2023

作者： Sun, Sixian Zheng, Qijia Ren, Liping An, Linxue He, Yufeng Han, Shuyue Beijing Precision Electromechanical Control Equipment Research Institute Aerospace Servo Drive and Transmission Technology Laboratory Beijing100076 China

ISBN: (纸本)9789819968817

In response to the problem of multiple iterations of the classic cordic algorithm and poor real-time performance of shaft angle conversion, a shaft angle digital conversion method based on the improved cordic algorithm is proposed. This method uses the improved cordic algorithm and closed-loop tracking algorithm to achieve high-precision shaft angle digital conversion;On this basis, an FPGA based shaft angle conversion testing system was built, and the application verification of this method was carried out. The experimental results showed that the shaft angle digital conversion method is correct, reliable, and has better dynamic characteristics. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023.

关键词： Axis angle digital conversion cordic algorithm Motor control

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Combining cordic algorithm and FPGA to Design Dual Core FFT Processor

Combining CORDIC Algorithm and FPGA to Design Dual Core FFT ...

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International Conference on Industrial Mechatronics and Automation

作者： Jiang Murong Yang Jun Guo Yuedong Du Xiaogang Li Na Yunnan Univ Sch Informat Sci & Engn Kunming 650091 Peoples R China

ISBN: (纸本)9781424438181

In this paper, the design for a dual core FFT processor based on cordic algorithm is presented. This design extracts the 2-base successions as the foundation, takes the FFT butterfly-shaped arithmetical unit as the object, uses the cordic algorithm superiority in the vector computation to simply the revolving factor calculation, and employs the assembly line technology to enhance the turnover rate for the whole system. This FFT processor has many characteristics with the simple hardware architecture, flexible disposition, low component coupling, high precision and stable running, can perform the high speed fixed-point real-time FFT operation. Experiment carried on the gate level simulation in Altera chip EP2C35F672C6 shows that this design can satisfy the 50MHz system clock.

关键词： FFT processor cordic algorithm BUF FPGA

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Improvement of cordic algorithm

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Journal of Beijing Institute of Technology 1998年第4期7卷 400-405页

作者：石晶林李滔于波张群英韩月秋北京理工大学电子工程系北京100081

Aim To discuss the basic cordic algorithm that can be applied to digital signal processing and its applying condition called convergence *** In addition to the original basic equation, another group iterative equation was used to evaluate the correspondent values of input data that did not lie within the convergence range. Results and Conclusion The improved cordic algorithm removes the limits of the range of convergence and can adapt itself to the variations of input values. The correctness of improved cordic algorithms has been proved by calculating examples.

关键词： convergence, iterative equation cordic algorithm

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An optimized hardware implementation of the cordic algorithm

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IEICE ELECTRONICS EXPRESS 2022年第21期19卷 20220362-20220362页

作者： Lyu, Fei Wu, Chaoran Wang, Yuxuan Pan, Hongbing Wang, Yu Luo, Yuanyong Jinling Inst Technol Sch Elect & Informat Engn Nanjing 211169 Peoples R China Nanjing Univ Sch Elect Sci & Engn Nanjing 210023 Peoples R China Nanjing Xiaozhuang Univ Sch Elect Engn Nanjing 211171 Peoples R China HiSilicon Huawei Corp Dept Turing Architecture Design Linx Lab Shenzhen 518129 Peoples R China

In this paper, we propose a software-based simulator and an optimized hardware implementation of the cordic algorithm. The number of iterations and the bit width are selected by their relationship calculated by the simulator to satisfy precision requirement. In the proposed hardware implementation, the addition and subtraction operations share the hardware resources. The two's complement is calculated in two steps: inverting and adding one. The adding one operation is integrated in the addition com-ponent of the iteration. In addition, a 3:2 compressor is used to reduce the number of adders, and a carry look-ahead adder is used to reduce the critical path. The synthesized results show that when compared with state-of-the-art designs, our method reduces the area by 53.79% and the delay by 58.97% while maintaining the same precision.

关键词： cordic algorithm software-based simulator iteration carry look-ahead adder

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Novel design for a low-latency cordic algorithm for sine-cosine computation and its Implementation on FPGA

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MICROPROCESSORS AND MICROSYSTEMS 2020年 77卷 103197-103197页

作者： Salehi, Forouzan Farshidi, Ebrahim Kaabi, Hooman Shahid Chamran Univ Ahvaz Fac Engn Dept Elect Engn Ahvaz Iran

This paper proposes a design of a fast FPGA based architecture for Coordinate Rotation Digital Computer (cordic) algorithm with reduced number of iterations. cordic is on such technique which uses just shift-add/sub operations. So, it widely has been used because its flexibility characteristics. However, the major disadvantage is its relatively slow computational speed due to the determination of rotation direction by analyzing the results of the previous iteration. The basic idea of this paper is to reduce the iteration number to overcome this shortcoming. Finally, the prototype based on FPGA architecture has been established to test the performance of the proposed design. The design is implemented in VHDL, synthesized on Xilinx Spartan6 xc6slx9-2tqg144 FPGA kit. The proposed architecture computes Sine and Cosine values in 3/8 n (n is the bit-width of operand) clock cycles and the maximum operating frequency of the proposed architecture is as fast as 108.120 MHz. The simulation and implementation results verify the authenticity of this design. (C) 2020 Elsevier B.V. All rights reserved.

关键词： cordic algorithm FPGA Alternate Low latency Multiplexer

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Optimization Design of cordic algorithm based on Vivado HLS

International Core Journal of Engineering

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International Core Journal of Engineering 2022年第8期8卷 833-836页

作者： Feng Xiao Dongcai Xie Xing Gan

Aiming at the shortcomings of traditional cordic algorithm for calculating trigonometric functions and taking up more resources, this paper studies a hardware acceleration method for cordic algorithm to calculate angle sine and cosine using Vivado HLS (High-Level-Synthesis). By constraining the generation parameters of RTL, the purpose of reducing computing delay and saving on-chip resources is achieved. The test results show that the cordic algorithm optimized based on Vivado HLS can achieve lower clock delay and lower resource utilization than the traditional implementation with the same number of iterations.

关键词： cordic algorithm Trigonometric Function Calculation Hardware Acceleration

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Research of Pipelined cordic algorithm and Implementation Based on FPGA

Research of Pipelined CORDIC Algorithm and Implementation Ba...

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2011云计算与信息技术应用学术会议

作者： Zhongming JI Xiaochen ZHAN School of Automation HangZhou Dianzi UniversityHangZhou310018ZheJiang

cordic algorithm can transform the complex operations，which are difficult to be directly implemented by hardware circuits，into the simple addition and shift operations uniformly，then gradually approach the accurate *** study gives a brief introduction of the ultimate principle and computing method of cordic *** sine and cosine as examples，the method of realization on FPGA is presented and it is of good arithmetic speed as a result of using *** design has been provided correct by simulating and verification through Quartus Ⅱ and Modelsim．

关键词： cordic algorithm pipeline FPGA

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Modified vector rotational cordic (MVR-cordic) algorithm and architecture

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING 2001年第6期48卷 548-561页

作者： Wu, CS Wu, AY Natl Cent Univ Dept Elect Engn Chungli 320 Taiwan Natl Taiwan Univ Dept Elect Engn Taipei 106 Taiwan

The cordic algorithm is a well-known iterative method for the computation of vector rotation. However, the major disadvantage is its relatively slow computational speed. For applications that require forward rotation (or vector rotation) only, we propose a new scheme, the modified vector rotational cordic (MVR-cordic) algorithm, to improve the speed performance of cordic algorithm. The basic idea of the proposed scheme is to reduce the iteration number directly while maintaining the SQNR performance. This can be achieved by modifying the basic microrotation procedure of cordic algorithm. Meanwhile, three searching algorithms are suggested to find the corresponding directional and rotational sequences so as to obtain the best SQNR performance. Three SQNR performance refinement schemes are also suggested in this paper. Namely, the selective prerotation scheme, selective scaling scheme, and iteration-tradeoff scheme. They can reduce and balance the quantization errors encountered in both microrotation and scaling phases so as to further improve the overall SQNR performance. Then, by combining these three refinement schemes, we provide a systematic design flow as well as the optimization procedure in the application of MVR-cordic algorithm. Finally, we present two VLSI architectures for the MVR-cordic algorithm. It shows that by using the proposed MVR-cordic algorithm, we can save 50% execution time in the iterative cordic structure, or 50% hardware complexity in the parallel cordic structure compared with the conventional cordic scheme.

关键词： cordic algorithm DSP MVR-cordic algorithm searching algorithms VLSI

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Implementation of cordic algorithm on FPGA Altera Cyclone

Implementation of CORDIC Algorithm on FPGA Altera Cyclone

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Telecommunications Forum

作者： Milica Ristovi? Slobodan Lubura Dejan Joki? Faculty of Electrical Engineering University of East Sarajevo Vuka Karad?i?a 30 71123 East Sarajevo Bosnia and Hercegovina

ISBN: (纸本)9781467329835

In paper is presented HDL Code generation of cordic algorithm in MATLAB/Simulink, using HDL Code generation tool, and its implementation on FPGA Altera Cyclone, using Altera Quartus II. There are also tested data types which cordic uses, as well as time which is need for sine or cosine calculation of given angle, depending on these data types. With this information cordic can be easily implemented in any digital system.

关键词： Simulink HDL Coder cordic algorithm FPGA

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Mixed Radix cordic FFT algorithm for OFDM WPAN Applications

Mixed Radix CORDIC FFT Algorithm for OFDM WPAN Applications

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International Conference on Energy, Communication, Data Analytics and Soft Computing

作者： Yogini Dilip Borole C. G. Dethe Electronics & Telecommunication National Institute of Electronics & Information Technology

ISBN: (纸本)9781538618882

This electronic record portrays the technique for usage of Fast Fourier transform for wireless communication systems, like OFDM, digital video broadcasting, digital audio broadcasting, and worldwide inter-operability for microwave access. The high speed and low area FFT algorithm using cordic and radix 2^5 calculation is proposed here. cordic is fundamentally DSP application yet here it is utilized for twiddle component augmentation. Radix 2^5 fft calculation is utilized for lessening of complex duplication. The proposed computation minimizes the amount of multipliers. Plot outlines show that the FFT arranged by the proposed framework shows a lower hardware with more quality than existing systems. Our designed has a working frequency up to 420.203 *** computation is executed in both MATLAB and in Xilinx on Virtex-5.

关键词： FFT IFFT Radix 2^5 FPGA cordic algorithm

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