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检索条件"主题词=CORDIC Algorithm"

共 146 条记录，以下是61-70 订阅

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FPGA Implementation of a High Speed VLSI Architecture for cordic

FPGA Implementation of a High Speed VLSI Architecture for CO...

引用

IEEE Region 10 Conference 2009

作者： Lakshmi, B. Dhar, A. S. Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

ISBN: (纸本)9781424445462

COordinate Rotation DIgital Computer (cordic) based digital signal processing has become an important tool in consumer, communications, biomedical, and industrial products, providing designers with significant impetus for porting algorithm into architecture. Unfolded implementations of cordic algorithm can achieve low latency for rotation and various functions such as division, multiplication, logarithmic and exponential functions. Since the programmable approaches continue to progress in providing cost effective and high performance solutions, this paper presents a low latency field programmable gate array implementation of an unfolded architecture for the implementation of rotational cordic algorithm. This type of computational device is highly suitable for the implementation of customized hardware in portable devices where large parallelism and low clock rate can be utilized to meet low power consumption requirement.

关键词： cordic algorithm rotation mode VLSI architecture redundant arithmetic

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A high-efficiency vector interpolator using redundant cordic arithmetic in power-aware 3-D graphics rendering

A high-efficiency vector interpolator using redundant CORDIC...

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7th International Conference on Parallel and Distrubuted Computing, Applications and Technologies

作者： Sung, Tze-Yun Shieh, Yaw-Shih Yu, Chun-Wang Hsin, Hsi-Chin Chung Hua Univ Dept Microelect Engn Hsinchu 30012 Taiwan Natl Formosa Univ Dept Comp Sci & informat Engn Huwei Township Yunlin 63208 Taiwan

ISBN: (纸本)9780769527369

High performance architectures can be designed for data intensive and latency tolerant applications by maximizing the parallelism and pipelining of the algorithm. The hardware primitives for 3-D rotation for high throughput 3-D vector interpolation are presented in this paper. The primitives are based on the cordic algorithm. The proposed architecture Of the 3-D vector interpolator using redundant cordic arithmetic is presented in this paper. The high-throughput 3-D vector interpolator is implemented by VLSI.

关键词： redundant cordic arithmetic cordic algorithm 3-D vector interpolation high-throughput

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Doppler ultrasonograph with cordic based spectrum analyzer for blood flow velocity estimation

Doppler ultrasonograph with CORDIC based spectrum analyzer f...

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1st Regional Conference of the IEEE Engineering-in-Medicine-and-Biology-Society/14th Conference of the Biomedical-Engineering-Society-of-India

作者： Dhar, AS Banerjee, S INDIAN INST TECHNOL DEPT ELECTR & ELECT COMMUN ENGN KHARAGPUR 721302 W BENGAL INDIA

ISBN: (纸本)078032711X

An ultrasonograph system for estimating flow velocity of blood in the vessels, is proposed which incorporates a spectrum analyzer for observing the Doppler shift occurred due to the flowing blood. The Doppler signal is extracted from the reflected ultrasonic wave by synchronous demodulation technique and then fed to an analog-to-digital converter through a sample-and-hold circuitry. The spectrum analyzer uses FPGA based signal processing chips realizing vector rotations utilising modified cordic algorithm for computing discrete Hartley transform which is a real valued alternative to discrete Fourier transform.

关键词： Doppler ultrasonography blood flow velocity spectrum analysis cordic algorithm discrete Hartley transform

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FPGA Implementation of Elementary Generalized Unitary Rotation with cordic Based Architecture Preliminary Results

FPGA Implementation of Elementary Generalized Unitary Rotati...

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30th NORCHIP Conference

作者： Misans, Peteris Derums, Uldis Kanders, Vents Riga Tech Univ Fac Elect & Telecommun Riga Latvia

ISBN: (纸本)9781467322232

This paper describes the first trial of implementation of generalized unitary Jacobi-like rotation (the device is called EGU-rotator, further referred to as rotator) purely based on the cordic algorithm into Altera's and Xilinx FPGAs. The basics and examples for factorization of the generalized rotation matrix (further, matrix) are given. The number of matrix shapes alternates in the range from 4 to 64 depending on the range of used angles (parameters). A unified algorithm for implementation of parametrical rotator is provided. Reconfigurable architecture of rotator is briefly described. The choice of architecture is determined by 3 addresses and they correspond to different shapes of the matrix. The comparison of device resources for different wordlengths, the number of cordic iterations and platforms is given. The complex rotator works approximately 3 times slower and consumes approximately 5 times more device resources than a single cordic rotator.

关键词： Unitary transforms unitary Jacobi matrix cordic algorithm FPGA

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Twiddle Factor generation using cordic Processor for Fingerprint Application

Twiddle Factor generation using CORDIC Processor for Fingerp...

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IEEE International Conference on Computer, Communication and Control (IC4)

作者： Shinde, Suraj N. SUK Kolhapur Maharashtra India

ISBN: (纸本)9781479981632

Fingerprint applications are widely used to identify person's authenticity. The frequency domain analysis of fingerprint plays an important role for authentication of noisy fingerprint images. This paper proposes a cordic algorithm: a unique computing technique suitable for solving trigonometric functions like sine, cosine and arctanto extract features of fingerprint image using FFT for perfect matching. The idea is to reduce the computational complexity of FFT using cordic processor. The cordic processor is hardware efficient which minimizes the computational complexity for twiddle factor computations. The FFT extract features of fingerprint and is implemented using cordic processor which consumes 390 LUTs on VIRTEX 4 FPGA.

关键词： cordic algorithm rotation and vectoring mode fingerprint FPGA

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Parallel cordic-like Architecture: For Fast Rotation Implementation

Parallel CORDIC-like Architecture: For Fast Rotation Impleme...

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IEEE Region 10 Conference on TENCON

作者： Lakshmi, B. Dhar, A. S. Natl Inst Technol Dept ECE Warangal 506004 Andhra Pradesh India Indian Inst Technol Dept E & ECE Kharagpur 721302 W Bengal India

ISBN: (纸本)9781457702556

In this paper, a new redundant scalable cordic-like architecture is proposed for the implementation of fast rotation. The sequential nature of the conventional cordic algorithm in determining the direction of rotations is eliminated by computing the directions from the target angle. The proposed architecture offers high regularity and modularity. Detailed comparisons with other contributions shows that the proposed cordic-like fast rotator achieves 40% to 80% latency improvement.

关键词： cordic-like fast rotator cordic algorithm rotation mode VLSI architecture

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Reduced Latency Square-Root Calculation for Signal Processing Using Radix-4 Hyperbolic cordic 5th

Reduced Latency Square-Root Calculation for Signal Processin...

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5th International Conference on Advanced Computing, Networking, and Informatics (ICACNI)

作者： Kumari, Aishwarya Acharya, D. P. Natl Inst Technol Dept Elect & Commun Engn Rourkela India

ISBN: (纸本)9789811086366;9789811086359

In this paper, we are extending the usage of cordic algorithm from trigonometric mode, which has been the primary use of it from a very long time, to hyperbolic mode. Here, we have implemented Radix '4' hyperbolic cordic in vectoring mode for fast and efficient computing of Square-Root of a number. The simulation results are implemented on FPGA platform. Based on simulation results, comparison of Radix '4' cordic with Radix '2' cordic is presented too.

关键词： Hyperbolic Trigonometric cordic algorithm Radix '4' Pipelined architectures

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Systolic cordic DCT: An effective method for computing 2D-DCT

Systolic cordic DCT: An effective method for computing 2D-DC...

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7th International Symposium on Signal Processing and Its Applications

作者： Khayatzadeh, A Shahhoseini, HS Naderi, M Iran Univ Sci & Technol Dept Elect Engn Tehran 16844 Narmak Iran

ISBN: (纸本)0780379462

The 2D-DCT is used in image and speech processing for real-time application. In this paper a new hardware method is proposed for computing 2D-DCT. The hardware employs systolic array for doing recursive equation and use a cordic algorithm for determining some part of computation. So the method is called systolic cordic DCT or SCDCT. Parallelism, which is inherently employed in systolic array, helps to reduce the computation time. Comparing previous systolic method, SCDCT has lower computation time and memory referencing and has acceptable accuracy.

关键词： systolic array cordic algorithm DCT

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cordic based Orthogonal Signal Generation with In-loop Moving Average Filter for Single Phase PLL Systems 47

CORDIC based Orthogonal Signal Generation with In-loop Movin...

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47th Annual Conference of the IEEE-Industrial-Electronics-Society (IECON)

作者： Muddasani, Satyanarayana Teja, A. V. Ravi Indian Inst Technol Ropar Dept Elect Engn Rupnagar Punjab India

ISBN: (纸本)9781665435543

In this paper, an Orthogonal Signal Generation (OSG) using cordic algorithm is proposed for Phase Locked Loop (PLL) in single-phase systems. The Proposed technique is to overcome the issues of Second Order Generalized Integrator-PLL (SOGI-PLL) in estimating frequency and phase during abnormal conditions (dc offset, harmonics, voltage sag and frequency drift) of the grid. The OSG using cordic algorithm along With a Moving Average based band rejection Filter (WMAF) as an inloop filter is used to attenuate the harmonic frequency components present in the quadrature axis component (V-q) of PLL during abnormal conditions of the grid. To test the effectiveness of the proposed algorithm, the grid voltage input (V-g) with several critical distortions are considered and a comprehensive analysis of the results for the SOGI-PLL, SOGI-PLL-WMAF, and Proposed PLL are presented. These results are simulated using MATLAB/SIMULINK and validated using an experimental setup designed in the laboratory. The frequency estimate and phase are obtained accurately using proposed algorithm under the normal and abnormal conditions of the grid.

关键词： Phase locked loops Orthogonal signal generation Second order generalized integrator cordic algorithm moving average filter in-loop filter grid synchronization

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cordic-based FFT Real-time Processing Design and FPGA Implementation 12

CORDIC-based FFT Real-time Processing Design and FPGA Implem...

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12th IEEE International Colloquium on Signal Processing & its Applications (CSPA)

作者： Tang, Aimei Yu, Li Han, Fangjian Zhang, Zhiqiang Natl Univ Def Technol Sch Elect Sci & Engn Changsha 410073 Hunan Peoples R China

ISBN: (纸本)9781467387804

This paper presents a designing scheme of high-speed real-time serial pipelined Fast Fourier Transform (FFT) processor on FPGA which is based on Coordinate Rotation Digital Computer (cordic) algorithm. The cordic algorithm will reduce the hardware complexity compared to the direct implementation of the butterflies using complex multipliers. Moreover, the design uses the butterflies of the radix-2 Decimation-In-Time (DIT) algorithm, the dual-port RAM and the pipelined structure, which will sufficiently increase the performances of the FFT processor. The simulation results show that compared with the same type of real-time FFT processor, the scheme presented in this paper reduces the hardware resource requirements of Adaptive Look-up Tables (ALUTs) and increase the Signal Noise Ratio (SNR) by about 25dB.

关键词： cordic algorithm FFT FPGA

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