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检索条件"主题词=CORDIC algorithm"

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Implementation of Frequency Domain Equalizer for Single Carrier Transmission

Implementation of Frequency Domain Equalizer for Single Carr...

引用

4th International Conference on Wireless Communications, Networking and Mobile Computing

作者： Gheorghiu, Valentin Kameda, Suguru Takagi, Tadashi Tsubouchi, Kazuo Adachi, Fumiyuki Research Institute of Electrical Communication Tohoku University Aoba-ku Sendai 980-8577 Katahira 2-1-1 Japan QUALCOMM Japan Inc. Dept. of Electrical and Communications Engineering Graduate School of Engineering Tohoku University Aramaki Aoba-ku Sendai 980-8579 6-6-05 Aza-Aoba Japan

ISBN: (纸本)9781424421077

Single-carrier (SC) transmission using frequency domain equalization (FDE) based on the minimum mean square error (MMSE) criterion is an efficient way to combat the effects of frequency selective fading. In this paper, we discuss several key aspects concerning the implementation of a frequency domain equalizer and propose a feasible design. One of the problems is the implementation of the division operator used to compute the equalization weights. The cordic algorithm was employed for this as it reduces the hardware overhead. The proposed design was implemented in a FPGA and the performance was evaluated through experimental data.

关键词： Single-carrier implementation FPGA cordic algorithm

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Digital Hardware Optimization for 1.5-GHz High-Speed DDFS 21

Digital Hardware Optimization for 1.5-GHz High-Speed DDFS

引用

2014 21st IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Asok, Keerthi S. Sahoo, Karuna P. Amrita Vishwa Vidyapeetham Univ Kollam Kerala India

ISBN: (纸本)9781479942428

This paper describes the design optimization and analysis of the digital hardware of a high-speed direct digital frequency synthesizer (DDFS) implemented using the NanGate 45nm Open Cell library. The digital blocks of the DDFS generate 13-bit accurate sinusoidal waveform in the frequency range of 0 - 500 MHz. The DDFS uses a 1.5 GHz input clock, a ROM-less phase to amplitude converter (PAC) based on the cordic algorithm, and has a frequency tuning resolution of 1 mHz. Fixed-point simulations and analysis were performed to obtain the finite hardware bit-widths to meet the desired Signal-to-Noise-Ratio (SNR) and Spurious-Free Dynamic Range (SFDR) performance. Multiple quantization schemes were compared and the optimum scheme, which meets the hardware timing constraints and the desired system performance, is selected for the final hardware implementation.

关键词： circuit optimisation direct digital synthesis cordic algorithm NanGate open cell library ROM-less phase-amplitude converter digital hardware optimization direct digital frequency synthesizer finite hardware bitwidth fixed point simulations frequency tuning high speed DDFS signal-to-noise-ratio sinusoidal waveform size 45 nm spurious-free dynamic range Computer architecture Frequency synthesizers Hardware Quantization (signal) Signal to noise ratio System performance Tuning

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Digital resonator fiber optic gyro based on a miniature laser source

Digital resonator fiber optic gyro based on a miniature lase...

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3rd Asia Pacific Optical Sensors Conference (APOS)

作者： Ma, Huilian Yu, Xuhui Jin, Zhonghe Zhejiang Univ Dept Informat Sci & Elect Engn Hangzhou Zhejiang Peoples R China

ISBN: (纸本)9780819490278

A resonator fiber optic gyro (RFOG) based on a fiber-coupled semiconductor DFB-LD with an FPGA-based digital processor is set up. A bias stability of 23deg/h over one hour is successfully demonstrated. This is the best result in long time stability reported to date, to the best of our knowledge, for the RFOG based on a miniaturized laser source.

关键词： Resonator fiber optic gyro cordic algorithm digitalization miniature laser source

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Angular solution to FPGA-based high speed synchro

Angular solution to FPGA-based high speed synchro

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20th Chinese Control and Decision Conference

作者： Li Mingwei Mao Zhen Sui Yongsheng Dalian Univ Technol Sch Elect & Informat Engn Dalian 116023 Peoples R China

ISBN: (纸本)9781424417339

Synchro is a kind of angular measuring devices with high reliability widely used in avigation, spaceflight, military affairs and other fields It aims to test positions, displacements and other angular information. cordic algorithm and its pipeline architecture were utilized by correcting the compensating factor based on FPGA. During the angular solution, we proposed a new method for angle mapping to accomplish the high speed solution to arctangent function. Mapping the angle divided into eight areas into one area ranged from 0 to 45 degrees uniformly. Hardware resources were saved as well. Programme was written by VHDL and proved true by implementing on the FPGA chip. In addition, the accuracy is high with the maximum absolute error of <= 0.01 degrees. High speed and real time angular solution realized accurately so as to enhance accuracy of testing placements and positions System with low cost, high speed and high accuracy comes true.

关键词： FPGA synchro cordic algorithm angle mapping

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High-precision design of DDS Based on FPGA

High-precision design of DDS Based on FPGA

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3rd Global Congress on Intelligent Systems (GCIS)

作者： Wang, Xiaochu Mei, Qiujun Guangdong Univ Technol Sch Electromech Engn Guangzhou Guangdong Peoples R China

ISBN: (纸本)9781467330725

In order to achieve the goal of higher accuracy of DDS, In this paper, we will concentrate to modify and improve pipelined accumulator and the ROM lookup table which is based on the cordic algorithm on the base of traditional DDS. And compared with the advantages and disadvantages of traditional algorithm, experiments have proofed that the cordic algorithm can solve the problems of disorder, decentralization, big truncation error and instability of the traditional DDS output signal and it can also save the hardware resources up to 30%. It has obvious advantages showed on the speed, accuracy and hardware resources of the system.

关键词： DDS accumulator cordic algorithm

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Arbitrary waveform generator based on direct digital frequency synthesizer

Arbitrary waveform generator based on direct digital frequen...

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4th IEEE International Symposium on Electronic Design, Test and Applications

作者： Hu, Weibo Lee, Chung Len Wang, Xin'an Peiking Univ Shen Zhen Grad Sch Sch Comp & Informat Engn Shenzhen Peoples R China Natl Chiao Tung Univ Dept Elect Engn Hsinchu Taiwan

ISBN: (纸本)9780769531106

Arbitrary Waveform Generator (AWG) is an important signal generation module in many applications such as communication and mixed signal testing. This paper describes an AWG based on Direct Digital Frequency Synthesizer (FFDS). The cordic algorithm with an iterative process and a pipeline plus parallel structure are used to implement the AWG whose frequencies and amplitudes of sinusoid waveforms in the arbitrary wave can be controlled by frequency control words (FCWs), initial vectors of cordic module respectively. Compared to the conventional AWG, it is flexible and saves much hardware.

关键词： arbitrary waveform generator direct digital frequency synthesizer cordic algorithm

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A Digital Pseudo Random Number Generator Based on a Chaotic Dynamic System 26

A Digital Pseudo Random Number Generator Based on a Chaotic ...

引用

26th IEEE International Conference on Electronics, Circuits and Systems (ICECS)

作者： Gomar, Sh. Ahmadi, M. Univ Windsor Elect & Comp Engn Windsor ON Canada

ISBN: (纸本)9781728109961

Chaotic based Pseudo Random Number Generators (PRNGs) have been very popular due to their unpredictable behavior. Hardware implementations of PRNG is used in many applications including cryptography, security and communication systems. Chaotic systems demonstrate an extreme sensitivity to variations in initial conditions and control parameters which makes it ideal for such applications especially cryptography. Due to this severe sensitivity, it is essential to implement the system with a sufficient accuracy while keeping the hardware cost as low as possible. An efficient and compact digital design is proposed for a PRNG based on a low-dimensional chaotic dynamic system. In this design, cordic algorithm has been used to reduce the hardware cost while maintaining the accuracy high. Experimental results and error measurements indicate a maximum error of 0.011 and RMSE of 0.0015 between the proposed digital circuits and the original chaotic system. The circuits have been synthesized for an Altera FPGA board. The results indicate that the circuits are successfully able to mimic the mathematical simulation counterpart. In addition, synthesis results verify that the proposed circuits take less than 1% of the target FPGA resources. Furthermore, Static Timing Analysis demonstrate a maximum frequency of 172.09 MHz for the proposed circuits. The proposed circuits can be employed in cryptography and security applications due to their compactness and high accuracy.

关键词： Chaotic Pseudo Random Number Generator (CPRNG) Chaotic systems Field Programmable Gate Array (FPGA) cordic algorithm

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Optimized Hardware Framework of MLP with Random Hidden Layers for Classification Applications 10

Optimized Hardware Framework of MLP with Random Hidden Layer...

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Conference on Machine Intelligence and Bio-Inspired Computation - Theory and Applications X

作者： Zyarah, Abdullah M. Ramesh, Abhishek Merkel, Cory Kudithipudi, Dhireesha Rochester Inst Technol NanoComp Res Lab Rochester NY 14623 USA Univ Baghdad Dept Elect Engn Baghdad 10071 Iraq

ISBN: (纸本)9781510600911

Multilayer Perceptron Networks with random hidden layers are very efficient at automatic feature extraction and offer significant performance improvements in the training process. They essentially employ large collection of fixed, random features, and are expedient for form-factor constrained embedded platforms. In this work, a reconfigurable and scalable architecture is proposed for the MLPs with random hidden layers with a customized building block based on cordic algorithm. The proposed architecture also exploits fixed point operations for area efficiency. The design is validated for classification on two different datasets. An accuracy of approximate to 90% for MNIST dataset and 75% for gender classification on LFW dataset was observed. The hardware has 299 speed-up over the corresponding software realization.

关键词： Multilayer Perceptrons ELM Classification cordic algorithm Random Hidden Layers

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FPGA-based optical distortion correction for imaging systems

FPGA-based optical distortion correction for imaging systems

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8th International Conference on Signal Processing

作者： Qiang, Lin Allinson, Nigel M. Univ Sheffield Dept Elect & Elect Engn Mappin St Sheffield S1 3JD S Yorkshire England

ISBN: (纸本)9780780397361

A novel algorithm for correcting optical spatial distortion in imaging systems is presented, together with the architectures implemented for FPGA-based hardware. Since coordinate transformation functions generally require square root and trigonometric functions. which are not easily calculated using FPGA hardware, the cordic (Coordinate Rotation Digital Computer) algorithms are employed for these function implementations. An effective pipelined implementation for the radius correction is also demonstrated. The hardware architecture of the spatial correction algorithm has been targeted successfully on a Xilinx Spartan 3 device using the minimum of slices. The experimental results show that the pincushion distortion correction algorithms produce a very low residual error.

关键词： spatial optical distortions pincushion distortion barrel distortion cordic algorithm FPGA hardware implementation

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Low Complexity Detector for STBC-VBLAST Architecture Based on SQRD Decomposition

Low Complexity Detector for STBC-VBLAST Architecture Based o...

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20th IEEE Symposium on Personal, Indoor and Mobile Radio Communications

作者： Cortez, Joaquin Bazdresch, Miguel Garcia, Armando ITSON Univ Dept Elect Engn Obregon Mexico ITSON Univ Dept Elect Engn Guadalajara Jalisco Mexico

ISBN: (纸本)9781424451234

In this work we propose a very low complexity OSIC detector based on Sorted QR decomposition (SQRD) for signal detection in hybrid STBC-VBLAST systems where the number of receive antennas is at least equal to the number of transmit layers. The proposed detector reduces the complexity by at least 50% compared with the conventional SQRD algorithm, and uses Givens Rotations implemented using cordic to calculate the QR decomposition. We show how the proposed detection scheme outperforms other recent detection schemes for STBC-VBLAST systems in terms of bit error rate and required complexity.(1)

关键词： MIMO Receivers Hybrid Space-Time Codes Givens rotations cordic algorithm

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