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检索条件"主题词=CORDIC algorithm"

共 146 条记录，以下是21-30 订阅

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IQ Imbalance Compensation based on cordic algorithm in VLC-OFDM System 10

IQ Imbalance Compensation based on Cordic Algorithm in VLC-O...

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10th International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery (CyberC)

作者： Liu, Peng Guo, Yarong Li, Yue Liu, Song North China Elect Power Univ Yangzhong Intelligent Elect Inst Beijing Peoples R China

ISBN: (数字)9781728109749

ISBN: (纸本)9781728109749

This study investigates the problem of in-phase and quadrature (IQ) imbalance in the visible light communication (VLC) system. The effectiveness of the blind compensation method based on coordinate rotation digital computer (cordic) algorithm against the IQ imbalance is discussed. We further verify the proposed compensation method with QPSK and 16QAM signals respectively, with simulated impairments caused by the light emitting diode (LED) nonlinearity. Additionally, the analysis of Monte Carlo simulation under the assumption of different signal-to-noise ratio (SNR) is showed where in some cases, the compensation intensity increases as the SNR increases.

关键词： LED nonlinearity IQ imbalance Visible light communication cordic algorithm

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Implementation of DCT using variable iterations cordic algorithm on FPGA 1

Implementation of DCT using variable iterations CORDIC algor...

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First International Conference on Computational Systems and Communications (ICCSC)

作者： Mane, Mansi Patil, Dhanshree Sutaone, Mukul S. Sadalage, Akshay Coll Engn Pune Dept Elect & Telecommun Pune Maharashtra India

ISBN: (纸本)9781479960132

cordic or CO-ordinate Rotation DIgital Computer is a fast, simple, coherent and powerful algorithm which is used for diversified Digital Signal Processing applications. In pursuance of speed and accuracy requirements of todays applications, we put forward variable iterations cordic algorithm. In this algorithm, to boost speed we can lessen number of iterations in cordic algorithm for specific accuracy. This enhances efficiency of conventional cordic algorithm which we have used to compute Discrete Cosine Transform for image processing. One Dimensional Discrete Cosine Transform is implemented by using only 6 cordic blocks which needs only 6 multipliers. Because of the simplicity in hardware speed of image processing on FPGA is raised. Further increase in speed can be achieved by concurrently processing number of macro-blocks of an image on FPGA.

关键词： DCT cordic algorithm FPGA

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FPGA Implementation of Fast and Area Efficient cordic algorithm

FPGA Implementation of Fast and Area Efficient CORDIC algori...

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International Conference on Communication and Network Technologies (ICCNT)

作者： Chinnathambi, M. Bharanidharan, N. Rajaram, S. Thiagarajar Coll Engn Dept Elect & Commun Madurai Tamil Nadu India

ISBN: (纸本)9781479962662

This paper presents the fast and area efficient cordic (Coordinate Rotation DIgital Computer) algorithm for sine and cosine wave generation. The concepts of pipelining and multiplexer based cordic algorithm is used todecrease the critical path delay and reducing the area respectively. A six stage cordic is implemented by two schemes followed by four methods, unrolled cordic and multiplexer based cordic with and without pipelining. The pipelining is included in four stages(excluding first and last stage). An 8-bit cordic algorithm for generating sine wave and cosine wave is designed, implementedand compared by all four methods on Xilinx Spartan3E (XC3S250E).

关键词： cordic algorithm FPGA Multiplexer Pipelining Unrolled cordic Sine/Cosine

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ASIC Implementation of Fixed-Point Iterative, Parallel, and Pipeline cordic algorithm 8th

ASIC Implementation of Fixed-Point Iterative, Parallel, and ...

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8th International Conference on Soft Computing for Problem Solving (SocProS)

作者： Jyothi, Grande Naga Debanjan, Kundu Anusha, Gorantla VIT Univ Vellore Tamil Nadu India GCT Coimbatore Coimbatore Tamil Nadu India

ISBN: (纸本)9789811500350;9789811500343

In this paper, we proposed a Coordinate Rotation Digital Computer (cordic) algorithm for efficient hardware implementation of mathematical functions which can be carried out in a wide variety of ways for many digital signal processing applications. The cordic is a single unified algorithm for calculating many elementary functions such as trigonometric, hyperbolic, logarithmic function, exponential functions, multiplication, division, and so on. In this paper, a novel low power, low area, and high throughput fixed-point cordic algorithms are proposed. The standard cordic is also implemented for comparing the synthesis results. The proposed architecture scaling has been done using low area and low-power Scale Factor Correction Unit (SFCU). A low ADP SQRT-CSLA based ADD/SUB unit is proposed to overcomed the disadvantages of the basic ADD/SUB unit used in the standard cordic. The ROM lookup table size is also reduced to half. Extensive simulations are performed to verify the functionality. The standard and proposed cordic architectures are simulated in cadence NC launch and synthesized in cadence RC tool using TSMC GPDK 45 nm technology and area, power, and delay are calculated. The area and power consumption of the proposed cordic architecture are less when compared with standard cordic design.

关键词： cordic algorithm Pipeline Parallel Digital signal processing

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High-Speed Single Precision Floating Point Multiplier using cordic algorithm 3

High-Speed Single Precision Floating Point Multiplier using ...

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3rd International Conference on Electrical, Electronics, Communication, Computer Technologies and Optimization Techniques (IGEECCOT)

作者： Yeshwanth, Balaji Venkatesh, Vutukuri Akhil, Repala Natl Inst Technol Dept Elect & Commun Engn Tadepalligudem Andhra Pradesh India

ISBN: (纸本)9781538651308

Floating point arithmetic has paramount necessity in computer systems. Floating point multiplier is appreciably used in numerous applications which yearn for speed. Generally, floating point multiplier requires 23X23 mantissa multiplication and 8-bit exponent addition. Thus, delay of the mantissa multiplication plays a crucial role in boosting the speed. In this paper, the prime proposal is to increase the speed of the single precision floating point multiplier by implementing mantissa multiplication using cordic algorithm and exponent addition using Kogge-Stone adder which results in increasing the speed by several folds. Further, the performance of floating point multiplier using cordic algorithm and VEDIC multiplier is contemplated in terms of area, delay and power. Floating point multiplier was designed in VHDL using XILINX ISE 14.7 and implemented in XILINX Spartan 6e board. The proposed idea has shown better performance in terms of speed.

关键词： cordic algorithm Kogge-Stone adder Parallel Prefixadder Vedic multiplier Single precision floating point multiplier

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Design and Implementation of cordic algorithm using Integrated Adder and Subtractor 6

Design and Implementation of CORDIC algorithm using Integrat...

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6th International Conference for Convergence in Technology (I2CT)

作者： Bhukya, Sreenivasu Inguva, Sharath Chandra Sreyas Inst Engn & Technol Dept ECE Hyderabad Telangana India St Peters Engn Coll Dept ECE Hyderabad Telangana India

ISBN: (纸本)9781728188768

cordic (Coordinate Rotation Digital Computer) has been designed and implemented in many variants in the past five decades where the different architectures of the algorithm were used in many diverse applications. cordic algorithm is a flexible shift and add algorithm having an important feature of reduced quantization errors in the case of higher word lengths when compared to other algorithms. The major issue with the algorithm is due to its linear rate convergence with the speed of iteration. Its overall performance is also affected due to repeated number of shift and adds operations and thereby leading to high power consumption. The main aim of this work is to use a new integrated adder and subtractor designed using reversible gates in the place of binary adders and subtractors used in the previous design. This improved cordic uses an architecture where the rotation angle is split into micro rotation angles, where these angle sets provides faster convergence by reducing the number of iterations. Overall performance of the proposed algorithm is implemented using variety of FPGA families like Virtex-4, Virtex-5 and Artix-7 devices with comparison to parameters like area, frequency and power consumed. It is compared with the Conventional cordic and LH cordic designs.

关键词： cordic algorithm Canonical signed-digit Hcub algorithm Integrated adder subtractor

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Performance of the cordic algorithm in I-Q modulators

Performance of the cordic algorithm in I-Q modulators

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6th IASTED International Conference on Communication Systems and Networks

作者： Benavente-Peces, Cesar Pardo-Martin, Jose M. Ortega-Gozalez, Francisco J. Univ Politecn Madrid EUIT Telecommun Dept Ingn Circuitos & Sistemas Ctra Valencia Km 7 Madrid 28031 Spain

ISBN: (纸本)9780889866959

This paper analyses the use of the cordic algorithm in I-Q modulators. The analyse highlights the computational advantages of using this algorithm and the drawbacks, focusing on the fixed point arithmetic problem. Two approaches are presented and their performance is discussed based on the frequency error met by each one. Along the discussion, comparison with other computationally efficient algorithms is presented.

关键词： I-Q modulator/demodulator cordic algorithm phase rotator

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Design and Implementation of an Efficient Modified cordic algorithm 4

Design and Implementation of an Efficient Modified CORDIC Al...

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4th IEEE International Conference on Signal and Image Processing (ICSIP)

作者： Xue, Yuan Ma, Zhongsong Chinese Acad Sci Technol & Engn Ctr Space Utilizat Beijing Peoples R China Chinese Acad Sci Ctr Space Utilizat Key Lab Space Utilizat Technol & Engn Beijing 100094 Peoples R China Univ Chinese Acad Sci Beijing Peoples R China

ISBN: (纸本)9781728136608

Coordinate Rotation Digital Computer (cordic) algorithm has greatly improved the efficiency of the hardware implementation of digital signal processing algorithms and other mathematical operations. While there exist quite a lot of redundant iterations in the Conventional cordic algorithm, this paper proposes a novel efficient modified cordic algorithm combining the Conventional cordic algorithm with the VSF cordic algorithm. And this new method has already been simulated and implemented on Cyclone IV FPGA. The results show that the number of iterations has been obviously reduced while the hardware resource consumption is also decreased to some extent.

关键词： cordic algorithm Sealing-Free FPGA

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Method and testing of shaft angle digital conversion based on improved cordic algorithm 19th

Method and testing of shaft angle digital conversion based o...

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19th Chinese Intelligent Systems Conference, CISC 2023

作者： Sun, Sixian Zheng, Qijia Ren, Liping An, Linxue He, Yufeng Han, Shuyue Beijing Precision Electromechanical Control Equipment Research Institute Aerospace Servo Drive and Transmission Technology Laboratory Beijing100076 China

ISBN: (纸本)9789819968817

In response to the problem of multiple iterations of the classic cordic algorithm and poor real-time performance of shaft angle conversion, a shaft angle digital conversion method based on the improved cordic algorithm is proposed. This method uses the improved cordic algorithm and closed-loop tracking algorithm to achieve high-precision shaft angle digital conversion;On this basis, an FPGA based shaft angle conversion testing system was built, and the application verification of this method was carried out. The experimental results showed that the shaft angle digital conversion method is correct, reliable, and has better dynamic characteristics. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2023.

关键词： Axis angle digital conversion cordic algorithm Motor control

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An Efficient High-Speed cordic algorithm Using Parallel-Prefix Adders (PPA)

An Efficient High-Speed CORDIC Algorithm Using Parallel-Pref...

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International Conference on VLSI, Communications, and Signal Processing (VCAS)

作者： Venkatesh, Vutukuri Yeswanth, Balaji Akhil, Repala Jatoth, Ravi Kumar Natl Inst Technol Dept ECE Tadepalligudem Andhra Pradesh India Natl Inst Technol Dept ECE Warangal Telangana India

ISBN: (纸本)9789813297753;9789813297746

Delay and Area ceases the actual potential of the modern gadgets. Although, human has sophisticated devices around him yet yearns to save time and space. So, this paper centers on the highly efficient cordic algorithm, known for its low-cost implementation in DSP algorithms. In an effort, to improve the algorithm further in terms of area and speed, comparative analysis has been done by replacing Ripple carry adder with Parallel-Prefix adders, namely, Brent-Kung adder, Han-Carlson adder and Kogge-Stone Adder. The algorithm was designed in VHDL using XILINX ISE 14.7 design suite and implemented in XILINX Spartan 6e FPGA. Obviously, Parallel-Prefix adders have shown improved performance.

关键词： cordic algorithm Ripple carry adder Carry look ahead adder Kogge-Stone adder Brent-Kung adder Han-Carlson adder

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