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Efficient Design and Implementation of Scale-Free cordic With Mutually Exclusive Micro-Rotations

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2025年第5期72卷 2243-2251页

作者： Meher, Pramod Kumar Aggarwal, Supriya C V Raman Global Univ Dept Comp Sci & Engn Bhubaneswar 752054 Odisha India IIIT Bhopal Bhopal 462003 Madhya Pradesh India

In this paper, a new approach to the design of a micro-rotation set for scale-free cordic is proposed. The sine and cosine functions of all the micro-rotation angles are realized by a simple shift or a shift-add operations which significantly reduces the hardware complexity. Besides, the micro-rotation set (except the first one) is designed to form mutually exclusive pairs. As a result of mutually exclusive micro-rotations, it is possible to reduce the required number of iterations to almost half for a given precision. Apart from that, the latency, as well as, the hardware complexity are also significantly reduced. A 9-bit fractional accuracy is obtained with just 5 iterations as against 13 iterations required by the conventional cordic. Suitable threshold angles are proposed to decide, using low-complexity comparators, whether a micro-rotation should be executed in a given iteration or can be skipped. The proposed circuits to determine the rotation conditions for different iterations involve either 2-bit or 3-bit comparators. The cordic circuit based on the proposed set of micro-rotations is shown to converge for any given angle of rotation. Furthermore, the proposed design involves significantly less logic, computation time, and latency than the best of the scale-free cordic circuits. When implemented on Xilinx FPGA (Field Programmable Gate Arrays), it requires 20% less area, offers higher operating frequency, and saves close to 19% power and 20% energy per computation over the latter.

关键词： Complexity theory Circuits Accuracy Vectors Pipelines Hardware Taylor series Reviews Power demand Matrix decomposition Arithmetic circuits cordic cordic algorithm cordic circuit scale-free cordic sinusoidal function

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Fpga implementation of an efficient phase shift beamformer for narrow band sub-GHz applications

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2025年第2期122卷 1-14页

作者： Jeyakumar, P. Sudhakar, K. Thanapal, P. Navaneethan, C. Meenatchi, S. M Kumarasamy Coll Engn Dept Elect & Commun Engn Karur 639113 Tamilnadu India Vellore Inst Technol Sch Comp Sci Engn & Informat Syst Vellore 632014 India

To improve the received signal strength beams are formed by multi-element arrays. These beams are focused on the direction of arriving signals, with an intention of maximizing the received signal power. The signals with noise and interference arrived from a distinct direction will be estimated by Uniform Linear Array (ULA) with 10 antenna elements. The earlier signal will be phase-shifted with the help of phase shift beamformer. The Coordinate Rotation Digital Computer (cordic) algorithm is used compute the vector angle in signal cluster. The cordic algorithm is employed determint the phase shift and frequency offset. The beamformer assumes that incoming signal are narrow banded, a phase shift can estimate the required delay and preserve the incoming signal strength. The beamformer circuit is designed in Xilinx Vivado for simulation and synthesized using both Virtex-7 device and their results are compared with exisiting methods, which is evidence that the proposed design is formidable pertaining to power and delay. This design can operate at 100 MHZ with total on-chip power consumption of 725 mW.

关键词： Phase shift beamformer Narrow-band cordic algorithm Virtex-7

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FPGA implementation of high-performance, resource-efficient Radix-16 cordic rotator based FFT algorithm

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INTEGRATION-THE VLSI JOURNAL 2020年 73卷 89-100页

作者： Changela, Ankur Zaveri, Mazad Verma, Deepak Indus Univ Inst Technol & Engn Ahmadabad Gujarat India Pandit Deendayal Petr Univ Dept ICT Gandhinagar Gujarat India Ahmedabad Univ Sch Engn & Appl Sci Ahmadabad Gujarat India

The fast Fourier transform (FFT) is an algorithm widely used to compute the discrete Fourier transform (DFT) in real-time digital signal processing. High-performance with fewer resources is highly desirable for any real-time application. Our proposed work presents the implementation of the radix-2 decimation-in-frequency (R2DIF) FFT algorithm based on the modified feed-forward double-path delay commutator (DDC) architecture on FPGA device. Need for a complex multiplier to carry out the multiplication of complex twiddle factors and large memory to store the twiddle factors are the main concerns for FFT implementation. Propose work aims to address these issues. In this work, a high-performance radix-16 COordinate Rotational DIgital Computer (cordic) algorithm based rotator is proposed to carry out the complex twiddle factor multiplication. Further, cordic needs only rotational angles to carry out complex multiplication, which reduces the need for large memory to store the twiddle factors. To compute the total rotation for n-bit precision, our proposed radix-16 cordic algorithm takes n/4 iteration as compared to n iteration of the radix-2 cordic algorithm. Our proposed architecture of the radix-2 decimation-in-frequency (R2DIF) algorithm is implemented on a Virtex-7 series FPGA. Further, the detailed comparison is presented between our proposed FFT implementation and other recently proposed FFT implementations. Experimental results suggest that proposed implementation has less latency and hardware utilization as compared to recently proposed implementations.

关键词： cordic algorithm FFT Double-path delay commutator (DDC) Canonical signed digit (CSD) Redundant arithmetic FPGA

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Hybrid cordic algorithms

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IEEE TRANSACTIONS ON COMPUTERS 1997年第11期46卷 1202-1207页

作者： Wang, SY Piuri, V Swartzlander, EE POLITECN MILAN DEPT ELECT & INFORMATI-20133 MILANITALY

Each coordinate rotation digital computer iteration selects the rotation direction by analyzing the results of the previous iteration. In this paper, we introduce two arctangent radices and show that about 2/3 of the rotation directions can be derived in parallel without any error. Some architectures exploiting these strategies are proposed.

关键词： cordic algorithm elementary function Givens transformation planary rotator cordic architecture

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Design and VLSI Implementation of a Robot Navigation Processor deploying cordic based Anti-collission algorithm with RFID Technology 11

Design and VLSI Implementation of a Robot Navigation Process...

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11th Annual IEEE India Conference (INDICON)

作者： Roy, Subhashis Bag, Joyashree Sarkar, Subir Kumar Jadavpur Univ Dept ETCE Kolkata India

ISBN: (纸本)9781479953646

Design of a multiplier-less Robot navigation processor with anti-collision and Coordinate Rotation Digital Computer (cordic) based algorithm has been presented. The processor, deploying low power wireless Radio Frequency Identification Detection (RFID) technology has been implemented as an efficient VLSI architecture. The hardware of the processor has been realized up to RTL schematic level and fits into a single chip. Xilinx ISE 14.3 design simulation tool and KINTEX-7 FPGA kit have been used for implementation purpose. The performance of the proposed processor has been compared with the existing processor and it reveals improvement in terms of speed, hardware requirement and delay.

关键词： Robot Navigation processor RFID Technology cordic algorithm Anticollision RTL schematic FPGA

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VLSI architecture for parallel radix-4 cordic

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MICROPROCESSORS AND MICROSYSTEMS 2013年第1期37卷 79-86页

作者： Lakshmi, B. Dhar, A. S. Natl Inst Technol Dept Elect & Commun Engn Warangal 506004 Andhra Pradesh India Indian Inst Technol Dept Elect & Elect Commun Engn Kharagpur 721302 W Bengal India

COordinate Rotation Digital Computer (cordic) algorithm is an iterative method for fast hardware implementation of the elementary functions such as trigonometric, inverse trigonometric, logarithm, exponential, multiplication and division functions in a simple and elegant way. This paper presents a regular and scalable VLSI architecture for the implementation of parallel radix-4 rotational cordic algorithm. Thorough comparison of the proposed architecture with the available architectures has been carried out to show the latency and the hardware improvement. Furthermore, the proposed architecture is coded for 16-bit precision using the VHDL language. The functionally simulated net list has been synthesized with 90 nm CMOS technology library and the area-time measures are provided. This architecture is also implemented using Xilinx ISE7.1i software and a Virtex device. (c) 2012 Elsevier B.V. All rights reserved.

关键词： cordic algorithm Parallel radix-4 Redundant arithmetic

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A robust low-power fsm cordic lms filter design for exponential noise removal in pacemaker

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INTERNATIONAL JOURNAL OF ELECTRONICS 2024年第12期111卷 2303-2323页

作者： Agnes Shiny Rachel, N. Rajakumar, G. Sri Krishna Coll Technol ECE 9-59Ramanujam NagarKuniamuthur Post Coimbatore 641008 Tamilnadu India Francis Xavier Engn Coll ECE Tirunelveli Tamilnadu India

Heart disease is identified to be the major reason for death worldwide as recorded by World Health Organization. The use of cardiac pacemakers was estimated to be around 1.14 million in the year 2016 and is expected to increase to 1.43 million by the year 2023. Based on the frequency of usage, the lifetime of a pacemaker can last between 6 to 10 years. To prolong the lifetime of the pacemaker, a low-power filter design is presented. The pulse that comes out of the pacemaker has exponential noise and myo-potential noise. The least mean square (LMS) filter with Co-ordinate Rotation Digital Computer (cordic) filters the exponential noise signal and retrieves the desired pace pulse. The cordic architecture used here is realised using FSM computational technique, because FSM offers a simple hardware circuitry. Digital circuits highly rely on clock signal to track the time and execution of functions that are programmed. This irreplaceable signal requires a control module that would make it more efficient and audacious. This is the prime reason for the evolution of clock gating technique. Similarly, the leakage power caused by the power source also requires attention. With the boom of deep submicron technologies, leakage power has started to occupy 30-50% of the total power consumption. Power gating technique helps to resolve this issue significantly. In this proposed method, integrated coarse-grained power and clock gating technique is employed to reduce the power dissipation of the LMS filter. A comparative study of Latch-, AND- and OR-based clock gating with forced transistor stacking and sleep transistor whose width and length are doubled from the rest of the complementary metal oxide semiconductors is also performed. The design is implemented using 250 nm CMOS technology. The implementation of clock gating technique has resulted in a 41.35% average reduction in dynamic clock power dissipation. The power gating technique has resulted in 26.08% reduction in static input

关键词： Clock gating power gating pacemaker cordic algorithm LMS filter

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Low complexity VLSI implementation of cordic-based exponent calculation for neural networks

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INTERNATIONAL JOURNAL OF ELECTRONICS 2012年第11期99卷 1471-1488页

作者： Aggarwal, Supriya Khare, Kavita MANIT Bhopal Dept Elect & Commun Engn Bhopal Madhya Pradesh India

This article presents a low hardware complexity for exponent calculations based on cordic. The proposed cordic algorithm is designed to overcome major drawbacks (scale-factor compensation, low range of convergence and optimal selection of micro-rotations) of the conventional cordic in hyperbolic mode of operation. The micro-rotations are identified using leading-one bit detection with uni-direction rotations to eliminate redundant iterations and improve throughput. The efficiency and performance of the processor are independent of the probability of rotation angles being known prior to implementation. The eight-staged pipelined architecture implementation requires an 8 x N ROM in the preprocessing unit for storing the initial coordinate values;it no longer requires the ROM for storing the elementary angles. It provides an area-time efficient design for VLSI implementation for calculating exponents in activation functions and Gaussain Potential Functions (GPF) in neural networks. The proposed cordic processor requires 32.68% less adders and 72.23% less registers compared to that of the conventional design. The proposed design when implemented on Virtex 2P (2vp50ff1148-6) device, dissipates 55.58% less power and has 45.09% less total gate count and 16.91% less delay as compared to Xilinx cordic Core. The detailed algorithm design along with FPGA implementation and area and time complexities is presented.

关键词： cordic algorithm exponents hyperbolic functions leading-one bit neural networks Taylor series

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Digital Synthesizer/Mixer With Hybrid cordic-Multiplier Architecture: Error Analysis and Optimization

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2009年第2期56卷 364-373页

作者： De Caro, Davide Petra, Nicola Strollo, Antonio G. M. Univ Naples Federico II Dept Elect & Telecommun Engn I-80125 Naples Italy

This paper describes a novel architecture for digital synthesizer/mixer (DSM). The operation performed by a DSM corresponds to a rotation of the input vector in the complex plane. The proposed architecture divides this rotation into three subrotations. The first one uses a few cordic stages, in which the rotation directions are in parallel computed with the help of a small lookup table. The cordic algorithm is employed also in the second sub-rotation, where the rotation directions are readily available after a simple recoding of the bits of the residual angle. The final rotation is multiplier based to reduce circuit latency and increase performances. A detailed error analysis and sizing methodology is given in this paper. It is shown that different versions of the architecture can be conceived by varying the dimensions of the second block and the topology of the third block. The proposed architecture exhibits very good performances, owing to the efficient carry-save implementation of cordic datapaths, the reduced lookup table, and the small size of multipliers. Implementations in a 0.25-mu m CMOS technology are presented in order to demonstrate the design methodology and to investigate the implementation tradeoffs.

关键词： Angle rotator cordic algorithm digital down-converter digital mixer digital synthesizer digital tuner digital upconverter direct digital frequency synthesizer (DDFS) mixer modulator quadrature modulator

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Optimisation of direct digital frequency synthesisers based on cordic

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ELECTRONICS LETTERS 2001年第21期37卷 1278-1280页

作者： Cardells-Tormo, F Valls-Coquillat, J Univ Politecn Valencia Dept Elect Engn E-46071 Valencia Spain Univ Politecn Valencia Dept Elect Engn EPSG Grao De Gandia 46730 Spain

Methods to simplify digital frequency synthesisers based on the co-ordinate rotation digital computer (cordic) algorithm are presented. Application of the-se methods leads to performance enhancement, compared with the topologies previously proposed in the literature. For a given output precision, hardware resources are reduced and spur-free dynamic range is increased.

关键词： optimisation direct digital frequency synthesiser spur-free dynamic range circuit topology Signal generators Optimisation techniques Other digital circuits circuit optimisation cordic algorithm signal processing direct digital synthesis

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