This paper presents a multiplierless discrete cosine transforms (DCT) design with approximate canonical signed digit (csd) encoding for image processing. Two approximation strategies on csd encoding are proposed in co...
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ISBN:
(纸本)9781728192017
This paper presents a multiplierless discrete cosine transforms (DCT) design with approximate canonical signed digit (csd) encoding for image processing. Two approximation strategies on csd encoding are proposed in constant multiplication. Based on these two coding approaches, an approximate DCT architecture is presented by taking advantage of the correlation between adjacent pixels of image data. Higher frequency coefficients are gradually ignored from the calculation due to the energy compaction property. Four approximate DCT architectures are thus proposed representing different accuracy levels. The proposed DCTs are implemented using 0.18 mu m standard CMOS process. The simulation results indicate that the proposed ADCT reduces 51.5% power and 30.0% area with a PSNR penalty of 1.6dB when compared with the traditional design. For lossy applications which allow lower computational accuracy, ADCT-III achieves 70.0% and 43.9% reduction on the power consumption and area, respectively, at a cost of 11.7 dB accuracy loss.
The area, speed and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digita...
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ISBN:
(纸本)9781424442973
The area, speed and power consumption of over-sampled data converters are governed largely by the decimation filters in Sigma-Delta Analog/Digital converters(ADC) and multiplication is the core operation of the digital filter, so the performance of digital system is determined by multiplication. This paper compares four different popular methods: Conventional multiplications and additions;full custom distributed arithmetic (DA) scheme;Add-and-Shift method with csd encoding;advanced sub-expression sharing algorithm. Each scheme is analyzed in detail including implementing process and the experimental results are given to evaluate each scheme. All of these implementations are aimed to implement using Design Compiler. Then this paper presents an optimized circuit for the decimation filter and the decimation filter for Sigma-Delta ADC is implemented using 0.35 mu m CMOS technology, with an approximate silicon area of 19mm(21).
Sigma-delta modulation based single-bit ternary DSP algorithms have been extensively studied in the literature. More recently, FPGA based design and analysis of ternary FIR filter with distributed arithmetic (DA) algo...
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ISBN:
(纸本)9783642289613
Sigma-delta modulation based single-bit ternary DSP algorithms have been extensively studied in the literature. More recently, FPGA based design and analysis of ternary FIR filter with distributed arithmetic (DA) algorithm have been reported in comparison equivalent multi-bit systems. In this paper. we present the design and synthesis of single-bit ternary and multi-bit (i.e., conventional) FIR filters using a more complex but efficient encoding technique called canonical signed digit (csd) in both pipelined and non-pipelined modes. Both filter types are coded into VHDL and synthesized using small commercial FPGA devices in Quartus-II. Synthesis results show that in pipelined mode single-bit ternary FIR filter offers approximately 90% better clock performance than multi-bit FIR filter. Single-bit ternary FIR filter achieved clock frequency of 370 MHz using Stratix-III device that can easily process a 6-MHz video signal transmission. The single-bit DSP systems are highly beneficial for mobile communication purpose.
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