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Design and FPGA implementation of multiplierless comb filter

INTERNATIONAL JOURNAL OF CIRCUIT THEORY AND APPLICATIONS 2017年第11期45卷 1497-1513页

作者： Barsainya, Richa Agarwal, Meenakshi Rawat, Tarun Kumar Netaji Subhas Inst Technol Div ECE Room 135Sect 3 Dwarka New Delhi India

The main objective of this paper is to design and implement minimum multiplier, low latency structures of a comb filter. Multipliers are the most area and power consuming elements;therefore, it is desirable to realize a filter with minimum number of multipliers. In this paper, design of comb filters based on lattice wave digital filters (LWDF) structure is proposed to minimize the number of multipliers. The fundamental processing unit employed in LWDF requires only one multiplier. These lattice wave digital comb filters (LWDCFs) are realized using Richards' and transformed first-order and second-order all-pass sections. The resulting structural realizations of LWDCFs exhibit properties such as low coefficient sensitivity, high dynamic range, high overflow level, and low round-off noise. Multiplier coefficients of the proposed structures are implemented with canonic signed digit code (CSDC) technique using shift and add operations leading to multiplierless implementation. This contributes in reduction of number of addition levels which reduces the latency of the critical loop. A field programmable gate array (FPGA) platform is used for evaluation and testing of the proposed LWDCFs to acquire advantages of the parallelism, low cost, and low power consumption. The implementation of the proposed LWDCFs is accomplished on Xilinx Spartan-6 and Virtex-6 FPGA devices. By means of examples, it is shown that the implementations of the proposed LWDCFs attain high maximum sampling frequency, reduced hardware, and low power dissipation compared with the existing comb filter structures. Copyright (c) 2017 John Wiley & Sons, Ltd.

关键词： digital signal processing comb filter field programmable gate array Lattice wave digital filter canonic signed digit code

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Design and Implementation of Fractional Order Integrator with Reduced Hardware 3

Design and Implementation of Fractional Order Integrator wit...

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3rd International Conference on Signal Processing and Integrated Networks (SPIN)

作者： Barsainya, Richa aggarwal, Meenakshi Rawat, Tarun Kumar Netaji Subhas Inst Technol Div Elect & Commun Engn New Delhi 110078 India

ISBN: (纸本)9781467391979

This paper proposes a novel methodology for design and multiplierless implementation of fractional order integrator (FOI) based on lattice wave digital filter using gravitational search algorithm (GSA). The FOI design problem is formulated as an optimization problem using the transfer function of lattice wave digital filter (LWDF). The realization of FOI using LWDF structure increases the accuracy of design due to its excellent properties and also it requires only N number of multiplier coefficients for Nth order FOI. Furthermore, the minimum hardware and low power dissipation of FOI, which are the main concern of efficient implementation is also presented in this paper. The design level area optimization of the proposed lattice wave digital FOI (LWDFOI) is done by converting constant multipliers into shifts and adds using canonical signed digit code (CSDC) technique. The proposed LWDFOI is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. Simulation results are accomplished to show the comparison of the proposed LWDFOI with recent literature. The performance of the proposed LWDFOI is also evaluated in terms of speed, i.e. maximum frequency, area (number of slices) and power consumption. The proposed LWDFOI have been found to outperform the existing ones reasonably well in low and mid frequency range.

关键词： Fractional order integrator lattice wave digital filter gravitational search algorithm canonic signed digit code Carry save adder

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FPGA implementation of Hilbert transformer based on lattice wave digital filters 4

FPGA implementation of Hilbert transformer based on lattice ...

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4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO)

作者： Aggarwal, Meenakshi Barsainya, Richa Rawat, Tarun Kumar Netaji Subhas Inst Technol Div Elect & Commun Engn New Delhi 110078 India

ISBN: (纸本)9781467372312

The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an effective way of implementing the lattice wave digital structure of the Hilbert transformer with canonic signed digit code (CSDC) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow ripple carry adders. This increases the speed of overall filter structure compared to the conventional way of implementing the filter with CSDC coefficients. The proposed Hilbert transformer is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.

关键词： Hilbert Transformer FPGA Lattice Wave digital Filter Carry-save adder canonic signed digit code

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Multiplier-less Implementation of Quadrature Mirror Filter 4

Multiplier-less Implementation of Quadrature Mirror Filter

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4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO)

作者： Barsainya, Richa Aggarwal, Meenakshi Rawat, Tarun Kumar Netaji Subhas Inst Technol Div Elect & Commun Engn New Delhi 110078 India

ISBN: (纸本)9781467372312

The minimum hardware and low power dissipation have always been the main concern for the efficient filter implementation. In this paper, an efficient way of implementing the lattice wave digital filter (LWDF) structure of the quadrature mirror filter (QMF) with canonic signed digit (CSD) coefficients is proposed. Further, the proposed structure is implemented using carry save adders rather than slow carry propagation adders. This increases the speed of the overall filter structure compared to the conventional way of implementing the filter with CSD coefficients. The proposed QMF is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.

关键词： QMF FPGA Lattice Wave digital Filter Carry-save adder canonic signed digit code

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Minimum Multiplier Implementation of a Comb Filter using Lattice Wave digital Filter 12

Minimum Multiplier Implementation of a Comb Filter using Lat...

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12 IEEE Int C Elect Energy Env Communications Computer Control

作者： Barsainya, Richa Aggarwal, Meenakshi Rawat, Tarun Kumar Netaji Subhas Inst Technol Div Elect & Commun Engn New Delhi 110078 India

ISBN: (纸本)9781467365406

The minimum hardware and low power dissipation are the main concern for efficient filter implementation. A method to design and implement the comb lattice wave digital filter with only one multiplier, small area and low power dissipation is proposed. Lattice wave digital filter is used for filter realization due to its excellent properties. A design level area optimization is done by converting constant multipliers into shifts and adds using canonical signed digit code (CSDC) technique. The filter is implemented and successfully tested on Xilinx Spartan XC3s200-4ft256 field programmable gate array (FPGA) device. The effectiveness of the proposed design method is proven with an example.

关键词： Comb Filter FPGA canonic signed digit code Carry save adder Lattice Wave digital Filter All-pass Filter

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Memristor-Based Redundant Binary Adder 2

Memristor-Based Redundant Binary Adder

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2nd International Conference on Engineering and Technology (ICET)

作者： El-Slehdar, A. A. Fouad, A. H. Radwan, A. G. Nile Univ NISC Res Ctr Cairo Egypt Cairo Univ Dept Engn Math Giza Egypt

ISBN: (纸本)9781479958078

This paper introduces a memristor based redundant binary adder for canonic signed digit code, that coding eliminates the carry and provides a carry-free addition. The proposed binary adder circuit tries to achieve high addition speed that is independent on the length of the data using the accumulation property of a Nano-element called a memristor. The general block diagram of the proposed circuit is illustrated based on memristors and its operation has been validated using HP memristor model and simulated via different examples using PSPICE showing a great match.

关键词： adders integrated circuit modelling memristor circuits HP memristor model PSPICE addition speed canonic signed digit code nanoelement redundant binary adder Adders Generators Integrated circuit modeling Memristors Oscillators Simulation Switches adders Memristors integrated circuit modelling SPICE Oscillators Switches dynamos simulating

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