检索结果-内蒙古大学图书馆

TRANslucent smart pixel ARray (TRANSPAR) chips for high throughput networks and SIMD signal processing

IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 1999年第2期5卷 316-329页

作者： Chen, CH Hoanca, B Kuznia, CB Sawchuk, AA Wu, JM Univ So Calif INtegrated Media Syst Ctr Inst Signal & Image Proc Los Angeles CA 90089 USA

We present a novel architecture for an optical network, TRANslucent Smart Pixel ARray (TRANSPAR), having smart pixel devices which effectively function in an optically translucent manner. The network protocol is similar to carrier-sense multiple-access/collision-detection (CSMA/CD) commonly used in Ethernet, but adapted to a ring configuration using optical parallel packets in free space. The TRANSPAR devices also function as a fine-grain mesh-connected parallel pipeline array for image and video signal processing. We designed, fabricated, and are currently testing the TRANSPAR smart pixel devices and network node hardware, This paper presents the network architecture, tradeoffs, and design decisions, the testing results to date, and ends with considerations on practicality and future scalability.

关键词： cellular logic arrays CMOS integrated circuits integrated optoelectronics optical networks smart pixels

来源：评论

学校读者我要写书评

暂无评论

Two-dimensional parallel pipeline smart pixel array cellular logic (SPARCL) processors - Chip design and system implementation

引用

IEEE JOURNAL OF SELECTED TOPICS IN QUANTUM ELECTRONICS 1999年第2期5卷 376-386页

作者： Kunzia, CB Wu, JM Chen, CH Hoanca, B Cheng, L Weber, AG Sawchuk, AA Univ So Calif Inst Signal & Image Proc Los Angeles CA 90089 USA

We describe the chip design and system implementation of an optoelectronic parallel pipeline processing system composed of cascaded stages of smart pixel array cellular logic (SPARCL) processors interconnected with free-space digital optic channels. The SPARCL processing elements are arranged in a two-dimensional array, and each contains an independent optical input/output port and electrical nearest-neighbor local interconnections. The smart pixels are implemented using GaAs-GaAlAs multiple quantum-well diode arrays flip-chip bonded onto complementary metal-oxide-semiconductor circuitry through the Bell Labs Lucent Technologies/George Mason University optoelectronic VLSI foundry, This system provides efficient execution of single-instruction multiple-data algorithms on large data fields and images.

关键词： cellular logic arrays CMOS integrated circuits integrated optoelectronics optical interconnections smart pixels

来源：评论

学校读者我要写书评

暂无评论

Effect of Mismatch on the Reliability of ON/OFF-Programmable CNNs

引用

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS 2009年第10期56卷 2259-2269页

作者： Laiho, Mika Brea, Victor Paasio, Ari Univ Turku Microelect Lab Turku 20014 Finland Univ Santiago de Compostela Dept Elect & Comp Sci Santiago De Compostela 15782 Spain

In this paper, the reliability of computation of ON/OFF-programmable cellular nonlinear networks (CNNs) is analyzed. This paper redefines the classical concept of robustness (tolerance to physical imperfections) in ON/OFF-programmable CNNs so that it can be used to predict the computation reliability of a physical realization. Also, a systematic approach to improve robustness is described, and guidelines for optimizing reliability with the given resources are given. Random mismatch is identified as the main source of errors in a physical realization. At the presence of random mismatch, we describe the probability of a cell producing an error with specific inputs and the error probability when processing random data. In addition, we show how the error probability could be defined in case the cell needs to work correctly with all possible input combinations.

关键词： Analog processing circuits cellular logic arrays cellular neural networks parallel architectures reliability estimation threshold logic

来源：评论

学校读者我要写书评

暂无评论

MINIMIZATION OF EXCLUSIVE OR AND logicAL EQUIVALENCE SWITCHING CIRCUITS

引用

IEEE TRANSACTIONS ON COMPUTERS 1970年第2期C 19卷 132-+页

作者： MUKHOPADHYAY, A SCHMITZ, G IEEE

This paper is an attempt to develop minimization algorithms for switching circuits based on Reed-Muller canonic forms. In particular, algorithms are presented for obtaining minimal modulo 2 or complement modulo 2 sum-of- products (or sums) expressions of any arbitrary single-output or multiple-output switching function with fixed polarities of the input variables.

关键词： APL cellular logic arrays maximal cliques of a graph miniimization algorithms modulo 2 sum-of- products (or sums) Reed-Muller canonic forms.

来源：评论

学校读者我要写书评

暂无评论

Wallpaper Computers: Thin, Flexible, Extensible and R2R Ready

Wallpaper Computers: Thin, Flexible, Extensible and R2R Read...

引用

Flexible Electronics and Displays Conference and Exhibition 2009

作者： Pavicic, Mark J. Ctr Nanoscale Sci & Engn Fargo ND 58102 USA

ISBN: (纸本)9781424443383

Wallpaper computers are thin flexible arrays of asynchronous programmable computing elements that can be produced in a roll-to-roll fashion. They have a regular structure that can be scaled in two dimensions to form various-size sheets of computing material. The asynchronous timing discipline ensures correct behavior regardless of the array size or variations in device properties. This new material can conform to the size, shape, and computational needs of a wide range of applications and may be implemented in a variety of technologies. Sheets may also be integrated with sensors, actuators, and emitters to create a wide variety of interactive intelligent surfaces. A light-sensitive wallpaper computer display is presented as an example. Status of ongoing work on CMOS designs of arrays of asynchronous reconfigurable cells with which to construct larger arrays is also mentioned.

关键词： asynchronous logic circuits cellular logic arrays flexible electronics LED displays programmable logic arrays roll-to-roll processing

来源：评论

学校读者我要写书评

暂无评论

Call for papers - Wireless Technology: Models, Designs and Applications

引用

IEEE Transactions on Electron Devices 2003年第4期50卷 1009-1014页

作者： A. Chimenton P. Olivo Dipartimento di Ingegneria Universitá di Ferrara Ferrara Italy

This paper presents experimental results and statistics about the erratic erase in Flash Memories, setting the basis for any physical modeling of the phenomena and data comparison. Statistical parameters like the reliability function and the failure rate have been measured and modeled by analytical functions showing that all cells of an array may potentially exhibit erratic events. By mapping the physical position of each erratic bit in a sector and using an equivalent cell approach, it has been possible to establish a correlation between the erratic phenomena and the intrinsic amorphous nature of SiO/sub 2/. Tail bits of the erased distribution have been shown to be caused by erratic events suggesting a unique physical cause for the two phenomena. The relation between positive and negative shifts has also been discussed and overerase risks caused by erratic behaviors have been estimated.

关键词： cellular logic arrays Integrated circuit reliability Integrated circuit modeling Statistics

来源：评论

学校读者我要写书评

暂无评论

2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM

引用

IEEE Transactions on Electron Devices 2001年第8期48卷 1599-1603页

作者： T. Endoh M. Suzuki H. Sakuraba F. Masuoka Research Institute of Electrical Communication University of Tohoku Sendai Japan

This paper proposes 2.4F/sup 2/ memory cell technology with stacked-surrounding gate transistor (S-SGT) DRAM. One unit of the S-SGT DRAM is formed by stacking several SGT-type cells in series vertically. The SGT-type cell itself arranges gate, source, drain and plate on a silicon pillar vertically. Both gate and plate electrode surround the silicon pillar. Subsequently applied trench etching and sidewall spacer formation during S-SGT DRAM formation causes a step-like silicon pillar structure. Due to these steps, gate, plate and diffusion layer in one S-SGT DRAM unit are fabricated vertically by a self-aligned process. The cell size dependence of the self-aligned-type S-SGT DRAM was analyzed with regard to the above step widths and the number of cells in one unit. As a result, the cell design for minimizing the cell size of this device has been formulated. By using the proposed cell design, it is demonstrated by process simulation that the S-SGT DRAM in 0.5 /spl mu/m design rule can achieve a cell size of 2.4F/sup 2/, which is half of the cell size of a conventional SGT DRAM cell (4.8F/sup 2/). Therefore, the S-SGT DRAM is a promising candidate for future ultra high density DRAMs.

关键词： cellular logic arrays

来源：评论

学校读者我要写书评

暂无评论

A universal digital VLSI design for neural networks

A universal digital VLSI design for neural networks

引用

International Joint Conference on Neural Networks (IJCNN)

作者： H.C. Fu J.N. Hwang S.Y. Kung W.D. Mao J.A. Vlontzos Dept. of Electr. Eng. Princeton Univ. NJ USA

Summary form only given. A universal digital VLSI design is proposed for implementing a wide variety of artificial neural networks. A programmable systolic array is presented based on a unified iterative neural network model, which maximizes the strength of VLSI in terms of intensive and pipelined computing and yet circumvents the limitation on communication. The array is meant for a universal simulation tool and neurocomputer architecture which can implement a variety of algorithms in both the retrieving and the learning phases of ANNs, e.g. single-layer feedback networks, competitive learning networks, multilayer feedforward networks, and stochastic neural networks. A fault-tolerance approach and partitioning scheme for large or nonhomogeneous networks are also proposed.< >

关键词： cellular logic arrays Learning systems Microprocessors Neural networks Pipeline processing Very-large-scale integration

来源：评论

学校读者我要写书评

暂无评论

A buried capacitor DRAM cell with bonded SOI for 256 M and 1 Gbit DRAMs

A buried capacitor DRAM cell with bonded SOI for 256 M and 1...

引用

International Electron Devices Meeting (IEDM)

作者： Nishihara Ikeda Aozasa Miyazawa Ochiai ULSI Research & Development Group Sony Corporation Atsugi Kanagawa Japan

This paper describes a novel DRAM cell structure using bonded SOI. The cell capacitor is flexibly formed like a stack-capacitor, but buried under the silicon layer. Thus, both a large Cs and small cell size are obtained. Moreover, using a PMOS cell transistor whose back-surface is shielded by a cell plate, the cell leakage current is reduced to 1 fA/cell, resulting in good data retention. Accordingly, a simple scaling of this structure realizes 256 M and 1 Gbit DRAMs.< >

关键词： cellular logic arrays DRAM chips MOS integrated circuits Semiconductor-insulator interfaces Very-large-scale integration

来源：评论

学校读者我要写书评

暂无评论

ICCAD-2005 International Conference on Computer Aided Design (IEEE Cat. No. 05CH37700)

ICCAD-2005 International Conference on Computer Aided Design...

引用

IEEE International Conference on Computer-Aided Design

The following topics are dealt with: memory and arithmetic optimization; design manufacturing interaction; circuit layout; digital analog and RF test; design for manufacturing; logic synthesis; double-gated devices; network routing and application specific NoC architectures; memory driven codes; arithmetic constructs; buffers and voltage islands; sequential circuit optimization; nanoelectronics; dynamic voltage scaling; biochips and DNA-based nanofabrication; circuit simulation; analog circuit design; power aware system architecture; software optimization; cellular array architectures; variability aware clocking; oscillator analysis; power noise and thermal issues; nanocomputing; extraction and modeling for interconnect structures; system-level variability modeling; high-level synthesis; model order reduction; statistical timing analysis; formal verification; hardware and software design of sensors; formal equivalence checking and system on chip.

关键词： Circuit optimization Digital arithmetic Routing Design methodology logic design Analog circuits cellular logic arrays Oscillators Design automation Reduced order systems Detectors

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：