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USE OF SYMBOLIC COMPUTATION IN ENGINEERING-EDUCATION

IEEE TRANSACTIONS ON EDUCATION 1995年第2期38卷 177-184页

作者： BELTZER, AI SHENKMAN, AL Center for Technological Education Holon Tel-Aviv University Holon Israel

The growing use of ''computer algebra'' (or ''symbolic computation'') makes it very attractive for employing in engineering education. Also the compromise between the analytic and numerical methods may be very useful. The objective of this paper is to draw the attention of broad engineering and educational circles to the enormous capabilities of symbolic computation and via a few examples show their application to the teaching of engineering.

关键词： Engineering education Voltage Application software Computer applications Computer science education circuit analysis computing Design automation Equations Impedance Admittance

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ESCAF FOR MTBF, TIME EVOLUTION, SENSITIVITY COEFFICIENTS, CUT-SET IMPORTANCE, AND NON-COHERENCE OF LARGE SYSTEMS

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IEEE TRANSACTIONS ON RELIABILITY 1986年第2期35卷 139-144页

作者： LAVIRON, A French Atomic Energy Commission (CEA) France

ESCAF - an "Electronic Simulator to Compute and Analyze Failures" - is a commercially available desktop apparatus, now in wide use, which employs special electronic circuit boards to simulate and analyze a system by methods and procedures that are easy to learn and apply by engineers with only very limited knowledge of electronics or computing. The apparatus has been used mainly to determine the cut sets and failure probabilities of very large systems, with up to 416 components, offering possibilities well beyond those of conventional methods of analysis. This article defines new parameters that can be calculated by ESCAF, including novel parameters (degree of non-coherence). It also explains how ESCAF determines, for systems of any complexity, measures that were previously inaccessible for other than very simple systems: . Mean time between failures, mean time to failure, mean time to repair, failure and repair intensities, and equivalent failure or repair rates as a function of time, . Time-derivative of the unavailability and/or failure probability, . Sensitivity coefficients indicating the importance of each component in probability calculation, . Importance of each minimal cut set (for coherent systems), . Whether a system is coherent or not. The first three results can be obtained regardless of system coherency. All results are obtained very simply and very rapidly.

关键词： Failure analysis Probability Design engineering Knowledge engineering Computational modeling Analytical models circuit simulation circuit analysis computing Reliability engineering Systems engineering and theory

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circuit modelling for electromagnetic compatibility

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ELECTRONICS & COMMUNICATION ENGINEERING JOURNAL 1997年第4期9卷 184-192页

作者： Darney, I J. S. Chinn Project Engineering Ltd. Speedwell Bristol BS5 7UZ Deep Pit Road United Kingdom

Sophisticated software is widely available in the form of mathematical and circuit analysis packages. This computing power can be harnessed to assess the electromagnetic coupling between signals in a system and currents in the structure. To achieve this objective, it is necessary to have reliable circuit models of the coupling parameters. A method of formulating such models is described, illustrating key relationships between circuit theory and electromagnetic theory. It is shown how general-purpose testing can be used to refine any model, and how the results of formal testing can be predicted.

关键词： formal testing circuit theory circuit testing circuit analysis package general-purpose testing electromagnetic compatibility Electromagnetic compatibility and interference electromagnetic theory Computer-aided circuit analysis and design coupling parameters circuit analysis computing electromagnetic coupling circuit models software

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PARALLEL circuit SIMULATION ON SUPERCOMPUTERS

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PROCEEDINGS OF THE IEEE 1989年第12期77卷 1915-1931页

作者： SALEH, RA GALLIVAN, KA CHANG, MC HAJJ, IN SMART, D TRICK, TN TEXAS INSTRUMENTS INC CTR SEMICOND PROC DESIGN DALLAS TX 75265 USA UNIV ILLINOIS COORDINATED SCI LAB URBANA IL 61801 USA ANALOG DEVICES INC DIV SEMICOND WILMINGTON MA 01887 USA

circuit simulation is a very time-consuming and numerically intensive application, especially when the problem size is large as in the case of VLSI circuits. To improve the performance of circuit simulators without sacrificing accuracy, a variety of parallel processing algorithms have been investigated. Research in the field of parallel circuit simulation is surveyed, and the ongoing research in this area at the University of Illinois is described. Both standard and relaxation-based approaches are considered. In particular, the forms of parallelism available within the direct method approach, used in programs such as SPICE2 and SLATE, and within the relaxation-based approaches, such as waveform relaxation, iterated timing analysis, and waveform-relaxation-Newton, are described. The specific implementation issues addressed are primarily related to general-purpose multiprocessors with a shared-memory architecture having a limited number of processors, although many of the comments apply to a number of other architectures

关键词： SLATE SPICE2 VLSI VLSI circuits circuit analysis computing general-purpose multiprocessors iterated timing analysis iterative methods numerically intensive application parallel circuit simulation parallel processing parallel processing algorithms relaxation theory relaxation-based shared-memory architecture waveform relaxation waveform-relaxation-Newton

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Effects of simultaneous switching noise on the tapered buffer design

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1997年第3期5卷 290-300页

作者： Vemuru, SR CUNY GRAD CTR NEW YORK NY 10031 USA

Complementary metal-oxide-semiconductor (CMOS) output buffers, comprised of a series of tapered inverters, are used to drive large off-chip capacitances. The ratio of the size of transistors between two consecutive stages is the buffer taper factor, With higher frequency of operation and simultaneous switching of the output drivers, the parasitic inductance present at the pin-pad-package interface results in significant switching noise on the power lines, A comprehensive analysis and estimate of simultaneous switching noise (SSN) including the velocity saturation effects seen in the submicron transistors during the switching of output drivers is presented, The effect of SSN on the overall buffer propagation delay and transition time is discussed, The presence of SSN results in an increase in the optimum taper factor between inverter stages for a given capacitive load. Beyond a critical value, the output transition time of a tapered buffer increases with reducing taper factor due to SSN. SSN can be reduced by skewing the switching of output buffers, SPICE simulation results show that skewing buffer snitching with additional inverter stages reduces SSN and increases buffer propagation delay.

关键词： Integrated circuit Noise Buffer circuits Integrated circuit Design CMOS Logic circuits VLSI Capacitance Inductance Delays SPICE circuit analysis computing Digital Simulation Logic CAD Simultaneous Switching Noise Tapered Buffer Design CMOS Output Buffers Off Chip Capacitances Parasitic Inductance Pin Pad Package Interface Velocity Saturation Effects Submicron Transistors Buffer Propagation Delay Inverter Stages Output Transition Time SPICE Simulation Inverters Propagation Delay Parasitic Capacitance Driver circuits Frequency Voltage circuit Noise Inductance Signal To Noise Ratio SPICE

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CAD-oriented fullwave equivalent circuit models for waveguide components and circuits

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1996年第12期44卷 2564-2570页

作者： Weisshaar, A Mongiardo, M Tripathi, A Tripathi, VK UNIV PERUGIA IST ELETTRI-06100 PERUGIAITALY

New multimode equivalent circuit models for single and cascaded E-plane and H-plane step discontinuities in rectangular waveguides are presented. The computer-aided design (CAD)-oriented equivalent circuit models enable rigorous and efficient fullwave analysis of waveguide components and circuits entirely by circuit simulation. The method has been implemented on the microwave circuit simulator Libra and applied to waveguide structures containing single and cascaded irises and stub discontinuities. Comparisons of circuit simulation results for single and cascaded inductive irises as well as a single and three E-plane stubs with the standard mode-matching method show perfect agreement, Results of a Ka-band bandpass filter analysis are in good agreement with a mode-matching solution that includes the correct edge condition.

关键词： CAD CAD-oriented circuit models cascaded irises circuit analysis computing circuit simulation Computational modeling computer-aided design Design automation E-plane step discontinuities edge condition electrical engineering computing equivalent circuits fullwave analysis fullwave equivalent circuit models H-plane step discontinuities inductive irises Ka-band bandpass filter analysis Libra microwave circuit simulator Microwave circuits Microwave theory and techniques Mode matching methods mode-matching method multimode equivalent circuit models Rectangular waveguides stub discontinuities waveguide circuits Waveguide components Waveguide discontinuities waveguide theory

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COMPUTER CALCULATION OF LARGE-SIGNAL GAAS-FET AMPLIFIER CHARACTERISTICS

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IEEE TRANSACTIONS ON MICROWAVE THEORY AND TECHNIQUES 1985年第2期33卷 129-135页

作者： MATERKA, A KACPRZAK, T Institute of Electronics Technical University of Lodz Lodz Poland

A simple and efficient method of GaAs FET amplifier analysis is presented. The FET is represented by its circuit-type nonlinear dynamic model taking into account the device's main nonlinear effects including gate-drain voltage breakdown. An identification procedure for extraction of the model parameters is described in detail and examples are given. The calculation of the amplifier response to a single-input harmonic signal is performed using the piecewise harmonic balance technique. As this technique is rather time-consuming in its original form, the optimization routine used to solve the network equations was replaced by the Newton-Raphson algorithm. Characteristics calculated with the use of the proposed method are compared with experimental data taken for a microwave amplifier using a 2SK273 GaAs FET unit. Good agreement at 9.5 GHz over wide ranges of bias voltage and input power levels are observed.

关键词： Gallium arsenide Microwave FETs Voltage Microwave devices Microwave theory and techniques Microwave oscillators Electrical engineering Microwave amplifiers circuit analysis computing Equivalent circuits

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GENTEST - AN AUTOMATIC TEST-GENERATION SYSTEM FOR SEQUENTIAL-circuitS

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COMPUTER 1989年第4期22卷 43-49页

作者： CHENG, WT CHAKRABORTY, TJ AT&T Bell Lab. Princeton NJ

A description is given of Gentest, with emphasis on STG2, a sequential test generator that uses the Back test-generation algorithm and the Split value model. The performance of STG2 on a Convex C-1 computer is compared with that of its predecessor, STG1 and STG1.5. Results are also presented for another set of experiments for Gentest on a Sun 3/60 workstation

关键词： BIST Back test-generation algorithm Convex C-1 computer Gentest STG2 Split value model Sun 3/60 workstation VLSI VLSI automatic test-generation system circuit analysis computing integrated circuit testing integrated logic circuits logic testing sequential circuits sequential circuits

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A DECOMPOSITION SCHEME FOR THE analysis OF FAULT-TREES AND OTHER COMBINATORIAL circuitS

引用

IEEE TRANSACTIONS ON RELIABILITY 1989年第3期38卷 312-&页

作者： HELMAN, P ROSENTHAL, A XEROX ADV INFORMAT TECHNOL CAMBRIDGEMA 02142

A new decomposition scheme for the analysis of fault trees and other more general combinatorial circuits is presented. The scheme is based on a tabular representation for the necessary information about a subsystem and generalizes the concept of modular decomposition. The basic algorithm is extended to obtain a very fast method for finding the sensitivity of the results to a large class of perturbations of the data. The scheme can be used to compute and analyze the sensitivity of many different types of measures on a circuit. The authors give a pair of axioms that capture sufficient conditions for the scheme to apply to computing a given measure and explicitly consider three different computational problems. A single algorithm is tailored to solve a new problem simply by supplying it with the necessary problem-specific subroutines. The efficiency of the algorithm depends on the choice of decomposition tree; the authors propose two simple heuristics for constructing a good decomposition tree. A theorem is obtained implying that if an efficient decomposition tree is found for the basic algorithm, the extended algorithm will also be efficient.< >

关键词： Fault trees Distributed computing Algorithm design and analysis Costs Information analysis circuit analysis computing Sensitivity analysis Combinational circuits Computational complexity Probability distribution

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GEOMETRIC CHARACTERIZATION OF SERIES-PARALLEL VARIABLE RESISTOR NETWORKS

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IEEE TRANSACTIONS ON circuitS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS 1994年第11期41卷 686-698页

作者： BRYANT, RE TYGAR, JD HUANG, LP IBM CORP DIV ADV WORKSTNAUSTINTX 78758

The range of operating conditions for a series-parallel network of variable linear resistors, voltage sources, and current sources can be represented as a convex polygon in a Thevenin or Norton half-plane. For a network with n elements of which k are variable, these polygons have at most 2k vertices and can be computed in O(nk) time. These half planes are embedded in the real projective plane to represent circuits with potentially infinite Thevenin resistance or Norton conductance. For circuits that have an acyclic structure once all branches to ground are removed, the characteristics polygons for all nodes with respect to ground can be computed simultaneously by an algorithm of complexity O(nk).

关键词： Resistors circuit analysis Voltage Computer networks Sensitivity analysis circuit analysis computing Optimization methods Books circuit theory

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