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Analysis of false lock in Mueller-Muller clock and data recovery system

INTEGRATION-THE VLSI JOURNAL 2025年 103卷

作者： Fang, Yahao Luo, Deng Liang, Bin Chen, Jianjun Chi, Yaqing Sun, Hanhan Sun, Qian Liu, Jingtian Natl Univ Def Technol Coll Comp Sci & Technol Changsha 410073 Peoples R China Natl Univ Def Technol Key Lab Adv Microprocessor Chips & Syst Changsha 410073 Peoples R China Acad Mil Sci PLA China Natl Innovat Inst Def Technol Beijing 100071 Peoples R China

As serializer/deserializer (SerDes) architectures evolve to support multi-Gbps data rates, Four-level Pulse Amplitude Modulation (PAM4) has emerged as the dominant signaling scheme owing to its superior spectral efficiency. However, the conventional Mueller-Muller clock and data recovery (MMCDR) architecture exhibits critical false lock artifacts when processing PAM4 signals, leading to significant degradation in Jitter Tolerance (JTOL) and Bit Error Rate (BER). Through theoretical analysis, we demonstrate that the root cause lies in the misalignment between the sampled signal and decision values during phase detection. To address this limitation, we introduce a novel Phase Detector (PD) architecture. A comprehensive CDR behavioral model integrating the proposed PD is developed in Simulink. Simulation results demonstrate that the improved PD avoids false lock compared to conventional MMPD implementations. Furthermore, the proposed PD achieves superior jitter tolerance performance. These advancements provide a hardware-efficient and readily implementable solution for high-speed PAM4 SerDes systems operating in lossy channels.

关键词： Phase detector clock and data recovery Four-level pulse amplitude modulation False lock

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A low-power 10Gb/s CMOS clock and data recovery circuit with a quarter-rate phase detector

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ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 2024年第2期119卷 269-282页

作者： Safari, Hamed Baghtash, Hassan Faraji Aghdam, Esmaeil Najafi Sahand Univ Technol Fac Elect Engn Tabriz *** Iran

A low-power clock and data recovery circuit with a quarter rate operating at 10 GHz is presented. This circuit consists of a phase lock loop and an input data retiming circuit. The phase-locked loop includes an LC oscillator, a quarter-rate detector, a charge pump, and a low-pass filter. The output of the oscillator is applied to a two-bit counter, so the clock frequency is reduced to 2.5 GHz with eight different phases which applied to the phase detector to sample the input data in different phases. Each sampling is done in 12.5 picoseconds. The innovative application of this two-bit counter eliminates the requirement of the multiphase oscillator, thus helps to reduce overall power dissipation. The power consumption of the voltage control oscillator is about 5.83 mW. In addition, reducing the clock frequency improves the performance of the phase detector circuit. The total power dissipation of the proposed CDR is evaluated to be 10.9 mW from a 1.8 V supply.

关键词： clock and data recovery Phase-locked loop Low-pass filter Two-bit counter

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Hybrid Timing Error Detector for Baud Rate Multilevel clock and data recovery

IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS

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IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS 2023年 4卷 324-335页

作者： Abdelaziz, Ahmed Ahmed, Mohamed Musah, Tawfiq Ohio State Univ Dept Elect & Comp Engn Columbus OH 43210 USA

This paper proposes a hybrid phase detector for use in multilevel timing recovery systems. The proposed approach suppresses errant zero-crossings associated with multilevel baud rate phase detectors and ensures maximum signal swing in lock, with minimal hardware and power overhead. Analysis and simulation results in a 28nm CMOS process are used to explore the functionality of proposed phase detector and demonstrate its effectiveness in achieving superior performance to the conventional approach. clock and data recovery (CDR) loop simulations show that the proposed phase detector enables 1.36 x increase in vertical eye margin while maintaining similar steady-state RMS jitter and compared to the conventional approach. The simulations also show effective suppression of unwanted phase detector zero-crossing, while achieving comparable acquisition bandwidth to the conventional approach.

关键词： Hybrid phase detection slope-sensitive latch time-domain interpolation multilevel signaling StrongArm latch clock and data recovery decision feedback equalizer

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A Wide-Range Reference-Less Digital clock and data recovery for Harmonic-Lock-Free Frequency Acquisition

A Wide-Range Reference-Less Digital Clock and Data Recovery ...

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IEEE International Symposium on Circuits and Systems (ISCAS)

作者： Lee, Hyun-Bin Heo, Yoon Lee, Won-Young Seoul Natl Univ Sci & Technol Dept Smart ICT Convergence Engn Seoul South Korea

ISBN: (纸本)9798350330991;9798350331004

This paper presents a digital clock and data recovery (CDR) designed for a faster approach to its steady-state and prevention of harmonic locking. By adopting a two-stage frequency detection system, the proposed CDR ensures a rapid and robust harmonic-lock-free frequency acquisition. The circuit is implemented and fabricated in a 28 nm CMOS process using a 1.0 V supply. The active area occupies 0.12 mm(2). It covers from 1.62 to 8.1 Gb/s, making it adaptable to embedded DisplayPort (eDP) interfaces. The prototype achieves the rms jitter and the peak-to-peak jitter is 5.54 ps(rms) and 27.53 ps(pp) at 8.1 Gb/s, respectively. Its lock time is reduced within 2 mu s for + 170% frequency error.

关键词： clock and data recovery fast locking anti-harmonic-lock all-digital reference-less

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An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate clock and data recovery 20

An Anti-Harmonic-Lock Frequency Detector for Continuous-Rate...

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20th International SoC Design Conference (ISOCC)

作者： Lee, Hyun-Bin Lee, Won-Young Seoul Natl Univ Sci & Technol Dept Smart ICT Convergence Engn Seoul South Korea

ISBN: (纸本)9798350327038

This paper presents a frequency detector (FD) for a continuous-rate clock and data recovery (CDR). The study analyzes the harmonic locking issue occurring in wide-range CDR and introduces the FD to prevent harmonic lock. It achieves anti-harmonic lock and fast lock time using coarse and fine frequency tuning. The conventional single-loop CDR incorporating the proposed FD is implemented and simulated in 65-nm CMOS technology. The capture range is 4-to-9 Gb/s and the locking time is shorter than 2 mu s for the maximum frequency offset of 7 GHz.

关键词： digital reference-less continuous-rate clock and data recovery anti-harmonic-lock

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Modeling the Performance of the clock Phase Caching Approach to clock and data recovery

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JOURNAL OF LIGHTWAVE TECHNOLOGY 2022年第6期40卷 1681-1689页

作者： Clark, Kari A. Liu, Zhixin UCL Dept Elect & Comp Engn London WC1E 6DH England

Optical switching could enable data center networks to keep pace with the rapid growth of intra-data center traffic, however, sub-nanosecond clock and data recovery time is crucial to enabling optically-switched data center networks to transport small packet dominated data center traffic with over 90% efficiency. We review the clock-synchronized approach to clock and data recovery, which enables sub-nanosecond switching time in optically switched networks. We then introduce an analytical model to mathematically explore the operation of clock phase caching, and use this model to explore the impact of factors such as fiber temperature, clock jitter and symbol rate on the BER and clock and data recovery locking time performance of the clock phase caching approach, as well as their impact on scalability. Using commercial data center parameters matching those used in our previous experimental research, we find that our analytical model provides estimates that closely match our previous experimental results, validating its use for making predictions of the performance of clock phase cached systems.

关键词： clocks Optical switches Optical transmitters Adaptive optics Optical receivers Synchronization Optical network units data center networks optical switching clock synchronization clock and data recovery clock phase caching

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A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang clock and data recovery in 22 nm FD-SOI CMOS Technology

A 28-Gb/s 27.2mW NRZ Full-Rate Bang-Bang Clock and Data Reco...

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IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS)

作者： Iftekhar, Mohammed Gowda, Harshan Kneuper, Pascal Sadiye, Babak Mueller, Wolfgang Scheytt, J. Christoph Univ Paderborn Heinz Nixdorf Inst Dept Syst & Circuit Technol Paderborn Germany

ISBN: (纸本)9798350307641

This paper presents a 28-Gb/s full-rate NRZ bangbang clock and data recovery (CDR) in 22nm FD-SOI CMOS technology. In order to reduce supply voltage and power dissipation, class-AB current-mode logic (CML) and forward-body biasing (FBB) are extensively used. Furthermore, the clock driver and clock path in the bang-bang phase detector are carefully optimized. The circuit operates reliably in a wide range of supply voltages from 0.8 to 1.2V without adjustment of the body biasing. The CDR core dissipates 27.2mW at 0.8V supply voltage and 54.4mW at 1.2V supply voltage. The recovered full-rate data surpasses jitter tolerance with a good margin (BER less than 10(-12)) over the entire supply voltage range. A figure-of-merit (FoM) of 0.97 mW/Gb/s for 0.8V supply voltage is achieved. This FoM represents the best FoM for full-rate NRZ bang-bang CDRs above 20 Gb/s and compares reasonably well with high-speed half-rate and quarter-rate NRZ CDR FoMs.

关键词： Bang-bang phase detector clock and data recovery latches FBB technique high-speed serial link

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Loop Dynamics Analysis of PAM-4 Mueller-Muller clock and data recovery System

IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS

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IEEE OPEN JOURNAL OF CIRCUITS AND SYSTEMS 2022年 3卷 216-227页

作者： Yadav, Kunal Hsieh, Ping-Hsuan Carusone, Anthony Chan Univ Toronto Edward S Rogers Sr Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada Natl Tsing Hua Univ Dept Elect Engn Hsinchu Taiwan

This paper provides a framework for analyzing the loop dynamics of the clock and data recovery (CDR) system of ADC-based PAM-4 receivers, which will assist in extending the timing recovery loop bandwidth. This paper formulates an accurate linear model of linear and signed Mueller-Muller phase detector for baud-rate clock recovery. Different equalization configurations of continuous-time linear equalizer (CTLE) and feed-forward equalizer (FFE) are evaluated from a phase detector performance perspective to enable high CDR loop bandwidth. The impact of loop latency on the timing recovery of ADC-based PAM-4 receivers is also analyzed and demonstrated using accurate behavioral simulations. The analysis and behavioral results show that, to achieve high CDR loop bandwidth with a good jitter tolerance, the phase detector gain to noise ratio should be maximized, and CDR loop latency should be minimized.

关键词： Detectors Timing Bandwidth Jitter clocks Standards Receivers Analog-to-digital converter (ADC)-based receiver clock and data recovery digital equalization feed-forward equalizer (FFE) time interleaving

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A 21.3-24.5 Gb/s low jitter PLL-based clock and data recovery circuit with cascode-coupled quadrature LC-VCO

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IEICE ELECTRONICS EXPRESS 2022年第24期19卷 6-6页

作者： Pan, Chengxian Shi, Chunqi Zhao, Guoliang Liu, Boxiao Huang, Leilei Zhang, Runxi East China Normal Univ Inst Microelect Circuits & Syst Shanghai 200241 Peoples R China China North Ind Grp Corp Res Inst 214 Bengbu 233000 Peoples R China

This paper presents a 21.3-24.5 Gb/s phase locked loop (PLL)-based reference-less clock and data recovery (CDR) circuit. A cascode-coupled technique is used in the design of the quadrature voltage-controlled oscillator (VCO), which eliminates the phenomenon of dual-mode oscilla-tion, provides a stable phase sequence for frequency acquisition and ensures the correct loop locking. The dual loop topology is adopted to realize a wide frequency acquisition range and an autonomous transition from fre-quency locking to phase locking, while the PLL-based structure brings in an excellent jitter performance. When the data rate of the input PRBS9 is 24.5 Gb/s, the measured peak-to-peak jitter and the root-mean-square (RMS) jitter of the recovered clock are 2.7 ps and 0.39 ps respectively, and the peak-to-peak jitter and the RMS jitter of the recovered data are 7.7 ps and 1.5 ps respectively. Implemented in 55-nm CMOS technology, the CDR circuit occupies a core area of 0.7 mm2 and consumes 170 mW at 1.2 V power supply.

关键词： PLL-based clock and data recovery dual-mode oscillation quadrature voltage-controlled oscillator (QVCO) dual-loop

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28nm Fault-Tolerant Hardening-by-Design Frequency Divider for Reducing Soft Errors in clock and data recovery

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IEEE ACCESS 2019年 7卷 47955-47961页

作者： Yuan, Hengzhou Guo, Yang Chen, Jianjun Chi, Yaqing Chen, Xi Liang, Bin Natl Univ Def Technol Coll Comp Sci Dept Microelect Changsha 410073 Hunan Peoples R China

A fault-tolerant hardening-by-design frequency divider has been proposed for clock and data recovery in a 28-nm CMOS process. By means of the mandatory updating mechanism, the proposed divider can update the state of the D flip-flops from an error state to a correct state so as to avoid single-event transient (SET) accumulation in different finite-state machines (FSMs). Our proposed divider also does not destroy the original structure and can, thus, greatly reduce performance degradation. Laser tests show that the threshold of the proposed divider can be significantly improved. The heavy-ion experiment shows good SET/single-event upset (SEU) tolerance during the ion strike under 83.7 ***(2)/mg.

关键词： clock and data recovery frequency divider hardening by design soft errors

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