In this day and age, successful embedded critical software needs agile and continuous development and testing procedures. This paper presents the overall testing and code coverage metrics obtained during the unit test...
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In this day and age, successful embedded critical software needs agile and continuous development and testing procedures. This paper presents the overall testing and code coverage metrics obtained during the unit testing procedure carried out to verify the correctness of the boot software that will run in the Instrument Control Unit (ICU) of the Energetic Particle Detector (EPD) on-board Solar Orbiter. The ICU boot software is a critical part of the project so its verification should be addressed at an early development stage, so any test case missed in this process may affect the quality of the overall on-board software. According to the European Cooperation for Space Standardization ESA standards, testing this kind of critical software must cover 100% of the source code statement and decision paths. This leads to the complete testing of fault tolerance and recovery mechanisms that have to resolve every possible memory corruption or communication error brought about by the space environment. The introduced procedure enables fault injection from the beginning of the development process and enables to fulfill the exigent codecoverage demands on the boot software.
Nowadays, the use of Systems-on-Chip (SoCs) represents a very interesting solution, but also introduces some testing concerns. Up to now, researchers focused many efforts on the development of new software and hardwar...
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ISBN:
(纸本)9781595938169
Nowadays, the use of Systems-on-Chip (SoCs) represents a very interesting solution, but also introduces some testing concerns. Up to now, researchers focused many efforts on the development of new software and hardware techniques for testing processors embedded in SoCs. However, the test of the surrounding peripherals has not been the subject of many research works, even if their importance within the entire system may be considerable. In this paper we focus on Software-based Self-Test techniques for testing peripheral components within a SoC and explore the possibility that test generation only relies on high-level metrics. We outline a possible test generation and application flow, and discuss the suitability of different RT-level metrics. By exploiting a sample case study, we quantitatively evaluate the effectiveness of the different metrics and the practical viability of the considered approach. As a major contribution, the paper shows that for peripheral components the relationship between high-level and gate-level metrics is higher than for the general case.
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