The results of a literature survey of human performance and coding techniques are presented. Recommendations are given for the application of coding techniques to the design of VDU formats (screen layouts) in a proces...
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The results of a literature survey of human performance and coding techniques are presented. Recommendations are given for the application of coding techniques to the design of VDU formats (screen layouts) in a process plant context. The coding techniques considered are colour, brightness, inverse video, flash, size and shape. The recommendations discuss the relative merits of the different techniques for presenting plant information, and the practical problems of applying a particular code. Some suggestions are given for further work.
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is b...
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ISBN:
(纸本)0769524060
As device geometries shrink, power supply voltage decreases, and chip complexity increases, the noise induced by the increased amount of simultaneously switching devices (especially the strong bus drivers (SSN)), is becoming crucial in determining the signal integrity of a system. In this paper we propose new ways of merging transition reducing coding techniques with coding techniques for fault tolerant busses (implementing either error detecting codes and error recovery, or correcting codes). In particular we focus on merging bus-invert code along with the employed error detection or correction coding technique, and show that the maximum number of simultaneous switching drivers can be drastically reduced, thus reducing the SSN and increasing signal integrity. Furthermore, we show how, by properly merging the bus invert encoder and the check bit generator, the latency introduced by the proposed coding techniques can be minimized and the number of additional wires can be kept minimal.
Two-dimensional magnetic recording (TDMR) is an emerging storage technology that aims to achieve areal densities on the order of 10 Tb/in 2, mainly driven by innovative channels engineering with minimal changes to exi...
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Two-dimensional magnetic recording (TDMR) is an emerging storage technology that aims to achieve areal densities on the order of 10 Tb/in 2, mainly driven by innovative channels engineering with minimal changes to existing head/ media designs within a systems framework. Significant additive areal density gains can be achieved by using TDMR over bit patterned media (BPM) and energy-assisted magnetic recording (EAMR). In TDMR, the sectors are inherently 2-D with reduced track pitch and bit widths, leading to severe 2-D intersymbol interference (ISI). This necessitates the development of powerful 2-D signal processing and coding algorithms for mitigating 2-D ISI, timing artifacts, jitter, and electronics noise resulting from irregular media grain positions and read-head electronics. The algorithms have to be eventually realized within a read/write channel architecture as a part of a system-on-chip (SoC) within the disk controller system. In this work, we provide a wide overview of TDMR technology, channel models and capacity, signal processing algorithms (detection and timing recovery), and error-correcting codes attuned to 2-D channels. The innovations and advances described not only make TDMR a promising future technology, but may serve a broader engineering audience as well.
Tables of irreducible polynomials and their exponents are listed for certain small nonprime Galois fields. These include all such polynomials up to and including degree 5 for GF(4), degree 3 for GF(8) and GF(9), and d...
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Tables of irreducible polynomials and their exponents are listed for certain small nonprime Galois fields. These include all such polynomials up to and including degree 5 for GF(4), degree 3 for GF(8) and GF(9), and degree 2 for GF(16). In addition, a single primitive polynomial is given for each degree up to and including degree 11 for GF(4), degree 7 for GF(8) and GF(9), and degree 5 for GF(16). A brief summary is given of several areas where these results may prove useful in providing an alternative to the more conventional approach.
A general method for designing two-layer neural networks which can be used as pattern classifiers is presented. The method is based on coding techniques. It is independent of the number of pattern elements and results...
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A general method for designing two-layer neural networks which can be used as pattern classifiers is presented. The method is based on coding techniques. It is independent of the number of pattern elements and results in a minimal-cost implementation for correcting and detecting random errors from black to white or from white to black. It can also detect all the unidirectional errors from white to black and all the unidirectional errors from black to white, preventing incorrectly recognized input images. It reduces the number of connections needed by the resulting neural networks by more than 80 % , as is shown in an example. compared with the other currently available methods.
The power used by the NoC resources increases as the number of processing elements rises. Due to the switching activities contained in the data bits being sent, NoC links are the main power dissipators in the NoC desi...
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As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated ...
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As device geometries shrink and power supply voltages decrease, simultaneous switching noise has increasingly detrimental effects on IC reliability. The authors investigate the worst-case conditions for SSN generated by a single switching wire and analyze the impact of transition-reducing encoding on SSN. They show that switching-pattern and layout considerations have a significant impact on TRE performance.
This paper introduces an effective technique for the compression of one-dimensional signals using wavelet transforms. It is based on generating a binary stream of 1s and 0s that encodes the wavelet coefficients struct...
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This paper introduces an effective technique for the compression of one-dimensional signals using wavelet transforms. It is based on generating a binary stream of 1s and 0s that encodes the wavelet coefficients structure (i.e., encodes the locations of zero and nonzero coefficients). A new coding algorithm, similar to the run length encoding, has been developed for the compression of the binary stream. The compression performances of the technique are measured using compression ratio (CR) and percent root-mean square difference (PRD) measures. To assess the technique properly we have evaluated the effect of signal length, threshold levels selection and wavelet filters on the quality of the reconstructed signal. The effect of finite word length representation on the compression ratio and PRD is also discussed. The technique is tested for the compression of normal and abnormal electrocardiogram (ECG) signals. The performance parameters of the proposed coding algorithm are measured and compression ratios of 19:1 and 45:1 with PRDs of 1% and 2.8% are achieved, respectively. At the receiver end, the received signal is decoded and inverse transformed before being processed. Finally, the merits and demerits of the technique are discussed. (C) 2002 IPEM. Published by Elsevier Science Ltd. All rights reserved.
Serial link interconnection has been proposed for its advantages of reducing crosstalk and area. However, serializing parallel buses tends to increase bit transition and power dissipation. Several coding schemes, such...
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Serial link interconnection has been proposed for its advantages of reducing crosstalk and area. However, serializing parallel buses tends to increase bit transition and power dissipation. Several coding schemes, such as serial followed by encoding (SE) and transition inversion coding (TIC), have been proposed to reduce bit transition. TIC is capable of decreasing transitions by 15% compared to the SE scheme, but an extra indication bit is added in every data word to represent inversion occurrence. The extra bit increases the transmission overhead and the bit transitions. This paper proposes an embedded transition inversion (ETI) coding scheme that uses the phase difference between the clock and data in the transmitted serial data to tackle the problem of the extra indication bit. The ETI coding scheme reduces the transition by up to 31% compared to SE scheme. The analysis and simulation results indicate that the proposed coding scheme produces a low bit transition for different kinds of data patterns. Using the optimum degree of multiplexing, width, and spacing, the ETI coding scheme achieves 30%-60% energy reduction compared with the parallel bus without overhead. Taking circuit overhead into consideration, the power saving is up to 31.71% and 26.46% at a clock cycle of 250 ps for the 90- and 130- nm CMOS technology for m = 2 where m is the number of parallel wires multiplexed into a serial link.
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