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compact model for MFIS-NCFETs considering deep-level interface trap states

JOURNAL OF COMPUTATIONAL ELECTRONICS 2024年第5期23卷 945-956页

作者： Liu, Xin Peng, Shaoman Lau, Heung Nung Huang, Xincheng Deng, Wanling Jinan Univ Dept Elect Engn Guangzhou 510630 Peoples R China Jixin Integrated Circuit Ind Res Inst Taihu Lake Lab Huzhou 313000 Peoples R China Huzhou Coll Dept Elect & Informat Huzhou 313000 Peoples R China

A direct current (DC) compact model for negative capacitance field-effect transistors (NCFETs) based on a metal-ferroelectric-insulator-semiconductor (MFIS) structure is proposed, considering the influence of deep-level interface trap states. To overcome the bottleneck problem of accurately and efficiently solving models, an explicit algorithm is developed, which is used to solve the complex Landau-Devonshire (LD) formula for the second-order phase transitions in physical models and the transcendental equation of trap density of states and surface potential. Compared with existing algorithms based on analytical surface potential, the new method does not require the numerical methods involving several iterations to obtain more accurate results, and the model can accurately reflect the opposite control effect of interface traps on surface potential and current under different ferroelectric (FE) thicknesses. The high precision of the model was verified through comprehensive numerical calculations and experimental data, indicating that the model can be effectively applied to circuit simulation design under low-power condition.

关键词： compact model Ferroelectric Negative capacitance field-effect transistor (NCFET) Subthreshold swing (SS) Surface potential Interface traps

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compact model Parameter Extraction via Derivative-Free Optimization

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IEEE ACCESS 2024年 12卷 123224-123235页

作者： Martinez, Rafael Perez Iwamoto, Masaya Woo, Kelly Bian, Zhengliang Tinti, Roberto Boyd, Stephen Chowdhury, Srabanti Stanford Univ Dept Elect Engn Stanford CA 94305 USA Keysight Technol Inc Santa Rosa CA 95403 USA Keysight Technol Inc Calabasas CA 91302 USA

In this paper, we address the problem of compact model parameter extraction to simultaneously extract tens of parameters via derivative-free optimization. Traditionally, parameter extraction is performed manually by dividing the complete set of parameters into smaller subsets, each targeting different operational regions of the device, a process that can take several days or weeks. Our approach streamlines this process by employing derivative-free optimization to identify a good parameter set that best fits the compact model without performing an exhaustive number of simulations. We further enhance the optimization process to address three critical issues in device modeling by carefully choosing a loss function that focuses on relative errors rather than absolute errors to ensure consistent performance across different orders of magnitude, prioritizes accuracy in key operational regions above a specific threshold, and reduces sensitivity to outliers. Furthermore, we utilize the concept of train-test split to assess the model fit and avoid overfitting. We demonstrate the effectiveness of our approach by successfully modeling a diamond Schottky diode with the SPICE diode model and a GaN-on-SiC HEMT with the ASM-HEMT model. For the latter, which involves extracting 35 parameters for the ASM-HEMT DC model, we identified the best set of parameters in under 6,000 trials. Additional examples using both devices are provided to demonstrate robustness to outliers, showing that an excellent fit is achieved even with over 25% of the data purposely corrupted. These examples demonstrate the practicality of our approach, highlighting the benefits of derivative-free optimization in device modeling.

关键词： Semiconductor process modeling Optimization Semiconductor device modeling Data models Data mining Computational modeling Numerical models Schottky diodes Parameter extraction SPICE HEMTs ASM-HEMT compact model derivative-free optimization device modeling diamond Schottky diode GaN HEMTs parameter extraction SPICE diode model

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A Comprehensive Physics-Based compact model for CNT Thin Film Transistors-Part I: Schottky Contact

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2024年第9期71卷 5709-5716页

作者： Tripathy, Srijeet Kumari, Ambika Bhattacharyya, Tarun Kanti Indian Inst Technol Adv Technol Dev Ctr Kharagpur 721302 India Indian Inst Technol Kharagpur Dept Elect & Elect Commun Engn Kharagpur 721302 India

We present a transistor model to describe the field effect current/voltage (I/V) relationship in single-wall carbon nanotube thin film transistors (CNT TFTs). Based on the nature of current transport, the model is subdivided to address Schottky contact and Ohmic contact CNT TFTs separately. In this part, the generalized theoretical model for the Schottky contact device is developed, and verified against experimental data. The primary aim of the model consists of determining the current across the CNT film, visualized as a network of interconnected CNTs. This is carried out by estimating the current across the individual CNTs and combining them using kirchhoff's current law (KCL) while following current continuity conditions. The device electrostatics are defined following a capacitive model where the effects of interfacial states, traps, charges, and so on are addressed. The effects of phonon scattering on transport are also discussed. From experimental results, phonon scattering is found to be greater at low drain and high gate biases. This is directly explained in terms of the energy band diagram of the device under the influence of external bias. The inferences drawn from this study are expected to also be extendable to other Schottky field effect transistor (FET)-based devices.

关键词： Carbon nanotube (CNT) CNT thin film compact model field effect transistor (FET) modeling phonon scattering Carbon nanotube (CNT) CNT thin film compact model field effect transistor (FET) modeling phonon scattering

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compact model of Conductive-Metal-Oxide/HfOx Analog Filamentary ReRAM Devices 50

Compact Model of Conductive-Metal-Oxide/HfOx Analog Filament...

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50th IEEE European Solid-State Electronics Research Conference (ESSERC)

作者： Galetta, Matteo Falcone, Donato Francesco Menzel, Stephan La Porta, Antonio Steccolini, Tommaso Choi, Wooseok Offrein, Bert Jan Bragaglia, Valeria IBM Res Europe Zurich Zurich Switzerland Politecn Torino Turin Italy PGI 7 Forschungszentrum Julich Germany

ISBN: (纸本)9798350388138;9798350388145

We pioneer a physics based compact model of analog filamentary conductive-metal-oxide (CMO)/HfOx ReRAM devices. Drawing from established physics-based models, we extend and customize them to explain the resistive switching mechanism in our analog ReRAM devices. Current transport in analog ReRAM devices involves carriers hopping through the localized defect states in the CMO layer, while in conventional filamentary ReRAM devices, it relies on ohmic and tunneling conduction. The model considers the ionic diffusion and drift currents as a function of the temperature dynamics and the electric field distribution. As the analog resistive switching arises from the redistribution of oxygen vacancies within a dome region in the proximity of the HfOx filament, we establish the time-dependent analytical description of the oxygen vacancy concentration in each resistance state. The compact model is validated using quasi-static voltage sweep data, resulting in a strong agreement between model predictions and experimental results.

关键词： Analog ReRAM Current transport Defects Conductive-Metal-Oxide Resistive switching compact model

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A Spatially Distributed Single Photon Avalanche Diode Verilog-A compact model

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2024年第1期71卷 331-336页

作者： Rink, Sven Kammerer, Jean-Baptiste Quenette, Vincent Uhring, Wilfried Gouget, Gilles Manouvrier, Jean-Robert Lallement, Christophe Ctr Natl Rech Sci CNRS ICube Lab F-67200 Strasbourg France STMicroelectron F-38920 Crolles France

Single photon avalanche diodes (SPADs) are crucial for Industry 4.0 advancements, especially in the design of LIght Detection And Ranging (LIDAR) sensors. A compact model is needed to accurately describe their transient behavior. This article presents a lumped model approach that divides the device into different regions. The model accurately emulates the behavior of reach-through SPAD photodiodes by dividing them into high electric field multiplication and low electric field absorption regions. The absorption region can be further subdivided to create multiple possible photon impact points, resulting in precise jitter modeling. This approach enables adaptable and unified SPAD modeling for different avalanche diode architectures. Experimental data confirm the accuracy of the model, and the characterization technique developed highlights the stochastic nature of the device.

关键词： Avalanche breakdown compact model experimentally validated model imaging industry 4.0 loop modeling single photon avalanche diode (SPAD) transient characterization Verilog-A

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Enhancement and Expansion of the Neural Network-Based compact model Using a Binning Method

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IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY 2024年 12卷 65-73页

作者： Choi, Jinyoung Jeong, Hyunjoon Woo, Sangmin Cho, Hyungmin Kim, Yohan Kong, Jeong-Taek Kim, Soyoung Sungkyunkwan Univ Coll Informat & Commun Engn Dept Semicond & Display Engn Suwon South Korea Sungkyunkwan Univ Coll Informat & Commun Engn Dept Elect & Comp Engn Suwon South Korea Samsung Elect Innovat Ctr Computat Sci & Engn Team Suwon South Korea Sungkyunkwan Univ Coll Informat & Commun Engn Dept Semicond Syst Engn Suwon South Korea

The artificial neural network (ANN)-based compact model has significant advantages over physics-based standard compact models such as BSIM-CMG because it can achieve higher accuracy over a wide range of geometric parameters. This makes it particularly suitable for design space exploration and optimization. However, the ANN-based compact model using only one set of model parameters (global-ANN) requires larger model sizes to achieve wider coverage and higher accuracy in order to capture the unpredictable nonlinearities of emerging devices. This results in reduced simulation speed and a trade-off between simulation accuracy, model coverage, and simulation speed makes it difficult to utilize ANN-based compact models in a variety of ways. To solve this problem, we propose the first ANN-based compact modeling flow using a binning method (binning-ANN) and we address the training requirements and data sparsity issues that may occur due to the binning method in ANNs. In addition, we develop a bin size optimization guideline for the binning-ANN. As a result, the binning-ANN not only has higher accuracy, but also much better expandability than existing methods.

关键词： Artificial neural network (ANN) machine learning (ML) device modeling compact model binning emerging device SPICE

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A compact model for Electro-Thermal Simulation of Resistive Random Access Memory With Graphene Electrode

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IEEE TRANSACTIONS ON NANOTECHNOLOGY 2024年 23卷 151-157页

作者： Zhai, Xingyu Li, Yun Yin, Wen-Yan Zhang, Shuo Zang, Wenxuan Yang, Yanbin Xie, Hao Chen, Wenchao Zhejiang Univ ZJU UIUC Inst Int Campus Haining 314400 Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Key Lab Adv Micro Nano Elect Devices & Smart Syst Hangzhou 310058 Peoples R China China Acad Space Technol Natl Key Lab Sci & Technol Space Microwave Beijing 100095 Peoples R China Zhijiang Intelligence Inst Chengdu Tianfu Dist Chengdu 610000 Peoples R China

Resistive random access memory (RRAM) with edge-contacted graphene electrode has much lower power consumption and excellent scalability as in other's previous studies, which shows great potential for in-memory computing, neuromorphic integrated circuits, Big Data analytics, etc. A physics-based SPICE compact model of RRAM with graphene electrode is proposed to capture the electro-thermal characteristics of the device with consideration of various physical effects in resistive switching processes, such as the temperature-dependent conductive filament (CF) evolution, tunneling between CF tip and electrode, graphene electrode oxidation, and self-heating effect. The equivalent thermal circuit (ETC) model is developed to capture the temperature response in RRAM. The influence of graphene electrode oxidation on the resistance of the device is taken into consideration. The compact model is verified by comparing the simulated characteristics of the set/reset process and forming process with other's published experimental data.

关键词： Graphene Electrodes Tunneling Metals Ions Conductivity Oxidation compact model equivalent thermal circuit Schottky emission graphene electrode resistive random access memory trap-assisted tunneling effect

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Event-Driven Stochastic compact model for Resistive Switching Devices

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2024年第8期71卷 4649-4654页

作者： Sune, J. Bargallo-Gonzalez, M. Saludes, M. Campabadal, F. Miranda, E. Univ Autonoma Barcelona Dept Engn Elect Cerdanyola Del Valles 08193 Spain Inst Microelect Barcelona IMB CNM CSIC Cerdanyola Del Valles 08193 Spain

A stochastic compact model for resistive switching (RS) devices is presented. The motivation is twofold: first, introducing variability in a natural way, and second, accounting for the discrete jumps of conductance observed during set and reset transitions. The model is based on an event generation rate, and it is an "on-the-fly" procedure because events are randomly generated as the simulation proceeds in time. For the generation of events, we assume a mixed nonhomogeneous Poisson process (NHPP). Before considering RS, we deal with the generation of successive breakdown (BD) events in metal-insulator-semiconductor structures. This confirms the validity of the approach by comparing it with experimental data in which discrete events are evident. To deal with RS, we transform a previous compact model into a stochastic model. Comparison with experiments in TiN/Ti/HfO2 /W devices shows the validity of the approach. Current-voltage loops and potentiation-depression transients in pulsed experiments are captured with a single set of parameters. Moreover, the model is an adequate framework to deal with both cycle-to-cycle and device-to-device variability.

关键词： Mathematical models Voltage Stochastic processes Switches Stress Computational modeling Europe compact model memristor resistive random access memorie (RRAM) resistive switching (RS) stochastic event generation

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A compact model for Interface-Type Self-Rectifying Resistive Memory With Experiment Verification

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IEEE ACCESS 2024年 12卷 5081-5091页

作者： Kim, Jin-Woo Beom, Jun-Seok Lee, Hong-Sub Kim, Nam-Seog Chungbuk Natl Univ Sch Informat & Commun Engn Cheongju 28644 South Korea Kyung Hee Univ Dept Adv Mat Engn Informat & Elect Yongin 17104 South Korea

Resistive random access memory (RRAM), a new non-volatile memory, enables hardware accelerators based on in-memory computing with improved throughput and energy efficiency, enabling machine learning on-the-fly inference at the edge. However, sneak-path currents in RRAM crossbar arrays (CBAs) can cause crosstalk, limiting high-density applications. The best choice for suppressing leakage current is self-rectifying RRAM (SRR). Interface-type RRAMs offer CMOS compatibility, better controllability, higher reliability, and lower power consumption compared to filament-type counterparts. However, while there is much research on the filament-type RRAMs, there is little research and no measurement validation on the interface-type RRAMs. In this paper, a compact model of the interface-type RRAM is developed for circuit and system exploration. The model includes Schottky barrier diode, effective layer resistance, nano-battery effect, parasitic resistance, and capacitance. It also has a dynamic behavior model, including device-to-device variation, retention, and endurance. Compared with measurements, it reproduces high accuracy of 98.97% in DC and 98.05% in AC. The proposed model is applied to a neuromorphic 64 x 64 SRR CBA with 32-bit fixed-point precision. A nano-battery bias scheme is also proposed to zero the current of RRAMs having non-zero I-V crossing points, reducing the sneak-pass current error to 0.02%. A vector matrix multiplication application demonstrates 3.44 TOPS/W with a 50:50 LRS to HRS ratio, and a deep neural network on a VGG-8 architecture using the CIFAR-10 dataset observes an accuracy degradation of 1.36%.

关键词： compact model crossbar array interface-type RRAM multiply and accumulate (MAC) nano-battery effect parasitic capacitance parasitic resistance resistive random access memory (RRAM) self-rectifying RRAM (SRR) vector matrix multiplication (VMM)

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Physical compact model for Source-Gated Transistors for DC Application

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IEEE TRANSACTIONS ON ELECTRON DEVICES 2025年第3期72卷 952-958页

作者： Golec, Patryk Bestelink, Eva Sporea, Radu A. Iniguez, Benjamin Univ Surrey Adv Technol Inst Sch Comp Sci & Elect Engn Guildford GU2 7XH Surrey England Univ Rovira & Virgili Dept Elect Engn Tarragona 43007 Spain

We present the first physical compact model for an amorphous silicon source-gated transistor (SGT) with variable Schottky barrier height. The previously published empirical compact model and TCAD model of an SGT are used to identify dominant effects present. The compact model is then validated on real device measurements. The compact model aims to operate under common conditions and typically desirable regimes of operation for an SGT, such as the flat saturation regime occurring at a particularly low saturation voltage. The dominant injection mechanisms occur through thermionic and thermionic field emission, which are the contact effects present in an SGT. Thermionic emission tends to be dominant under most common conditions. The model is suitably accurate to be used as a representation of an SGT in a SPICE simulation. This can be seen as a first step toward analog circuit design with SGTs as compact models enable circuit designers to utilize new and unique devices.

关键词： Mathematical models Thin film transistors Schottky barriers Thermionic emission Logic gates Transistors Integrated circuit modeling Semiconductor device modeling Semiconductor device measurement SPICE compact model Schottky barrier source-gated transistor (SGT) thin-film transistor (TFT)

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