complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore'...
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complementary field-effect transistors (CFETs), which are structures in which different types of transistors are vertically stacked with a shared control gate, are being focused on for continuing to satisfy Moore's law by overcoming the limitations in pitch scaling. The structures of semiconductor devices become more complex as technology node shrinks, and interrelated multivariate parameters increase. In addition, predicting problems and proposing solutions by identifying complex patterns within extensive data collected for emerging semiconductor designs pose significant computational challenges and are inherently difficult. As a breakthrough in design technology co-optimization for advanced devices, this study developed a novel optimization framework integrating technology computer-aided design simulations, machine learning, and non-dominated sorting genetic algorithms. The developed framework provides unbiased optimal solutions, even in a high-dimensional objective space, while considering the tradeoff relationships between multiple variables. In addition, it enables inverse design to identify the design parameters of devices that satisfy specific electrical performance criteria using only a forward model, while achieving an error rate of less than 2%. Using this framework, we analyzed the operational mechanism of CFETs by comparing the inverse designs of various devices. This novel approach is particularly important when the design space is complex and extensive and is well suited for developing devices that emerge with technological advancements in the semiconductor industry.
This study investigates a micro light-emitting diode (mu LED) pixel circuit using the heterogeneous integration of complementary field-effect transistors (CFETs). The CFETs are fabricated using a semiconductor layer c...
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This study investigates a micro light-emitting diode (mu LED) pixel circuit using the heterogeneous integration of complementary field-effect transistors (CFETs). The CFETs are fabricated using a semiconductor layer composed of tellurium (Te) and indium-gallium-zinc oxide (IGZO) layers. Te and IGZO layers in the heterostructure IGZO/Te film exhibit hexagonal and amorphous phases, respectively, indicating that each layer maintains independent material characteristics. The fabricated IGZO/Te CFETs exhibit ambipolar behavior with a turn-on voltage of 2.0 V and field-effect mobility of 0.74 and 1.42 cm2 V-1 s-1 for p-type and n-type channels, respectively. Inverters comprising IGZO/Te CFET and IGZO TFT exhibit inverting behavior. A mu LED pixel circuit is designed using IGZO/Te CFETs based on pulse width modulation (PWM). The proposed circuit uses an inverter structure with IGZO/Te and IGZO to control the emission time, suppressing the wavelength shift of mu LEDs depending on the mu LED current levels. The operation of the proposed pixel circuit is investigated through simulation and measurement of the fabricated circuit. The fabricated mu LED pixel circuit successfully exhibits PWM operation, controlling the emission time and luminance. Consequently, IGZO/Te CFETs show promise as devices for high-quality mu LED displays.
In this paper, two substrate optimization approaches for triple stacked nanosheet field-effecttransistors (SNSHFETs), namely the optimization of buried oxide and the selective deposition of punch-through-stopper (PTS...
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In this paper, two substrate optimization approaches for triple stacked nanosheet field-effecttransistors (SNSHFETs), namely the optimization of buried oxide and the selective deposition of punch-through-stopper (PTS) substrate, have been examined, and simulations have been carried out using technology computer-aided software. A comprehensive study of the leakage current and key electrical characteristics (ION, VT, subthreshold swing, drain-induced barrier lowering) has also been performed based on variations in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of the SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the VT and ION/IOFF ratio. The GIDL current also increases with increased doping of the source and drain. The impact of ultra-thin body substrate in the SNSHFET is also studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in the inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed in the channel-drain and gate-substrate overlap regions to understand the physical insights of leakage current in the SNSHFET. This work also clarifies the dependency of the GIDL current on the gate and drain voltage supply, respectively. In addition, how the GIDL current responds to the variation in the source-drain doping and with different PTS doping has been explained. A 3 nm SNSHFET is designed and its electrical and GIDL characteristics are compared with those of novel devices such as the forksheet FET and complementary FET.
We report the first demonstration of a high-temperature-tolerant complementary field-effect transistor (FET) inverter using a monolithic integration of n-channel gallium nitride (GaN) and p-channel diamond. The operat...
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We report the first demonstration of a high-temperature-tolerant complementary field-effect transistor (FET) inverter using a monolithic integration of n-channel gallium nitride (GaN) and p-channel diamond. The operation of the inverter up to 250 degrees C was recorded. A key feature of this work originates from the successful epitaxial growth of p-channel hydrogen-terminated polycrystalline diamond FET on an AlGaN/GaN high-electron-mobility-transistor structure, which then could be coprocessed to realize the inverter. The device stability in the diamond FET was achieved with a similar to 45 nm-thick atomic layer deposition of Al2O3 at 450 degrees C, serving as the gate dielectric as well as passivation for both diamond and GaN transistors. The process window of the coprocessing diamond and AlGaN/GaN was explored extensively to current match the two FETs.
As the scaling of integrated circuits based on silicon semiconductors becomes increasingly challenging due to the minimum feature size being close to the physical limit, the urgent demand for alternative strategies ha...
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As the scaling of integrated circuits based on silicon semiconductors becomes increasingly challenging due to the minimum feature size being close to the physical limit, the urgent demand for alternative strategies has fuelled the rapid growth of techniques and material innovations. Here, we report on the fabrication of vertically stacked ambipolar complementary field-effect transistor that is fully composed of two-dimensional materials of WSe2/h-BN/graphene/h-BN/WSe2 heterostructures. The ambipolar feature of the top and bottom WSe2 FET enables a switchable inverter behavior with a favorable voltage gain of up to 75, which can work in both the first and third quadrants. Based on the switchable characteristics, a large voltage swing circuit for single photon avalanche detectors is proposed without any bulky negative-voltage components. This work could open a new pathway for future two-dimensional electronics and ultimate monolithic 3D high-density integration circuits.
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