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Multi-channel Detector Module for Multi-energy Gamma Ray Computed Tomography

JOURNAL OF SIGNAL PROCESSING SYSTEMS FOR SIGNAL IMAGE AND VIDEO TECHNOLOGY 2022年第4期94卷 349-360页

作者： Bieberle, Andre Berger, Ronny Stave, Philipp Hampel, Uwe Helmholtz Zentrum Dresden Rossendorf Inst Fluid Dynam Bautzner Landstr 400 D-01328 Dresden Germany Tech Univ Dresden Chair Imaging Tech Energy & Proc Engn D-01062 Dresden Germany

In this paper an enhanced signal processing electronics for an existing multi-channel detector module for gamma ray computed tomography is presented. The detector electronics is able to evaluate gamma photon energies by measuring pulse duration times, which makes it perfectly suitable for attenuation measurements with multi-energy and/or multiple isotopic sources. The duration time of each voltage pulse generated by a gamma photon within the radiation detector is measured using a complex programmable logic device. A sophisticated logic circuit for eight detector channels is designed to acquire the pulse duration time spectra in a total of 256 channels per detector channel in parallel. This paper introduces the basic concept, describes the general and a specific CPLD design, provides an analysis of the accuracy and presents measured pulse duration time spectra.

关键词： Gamma ray computed tomography Radiation detection complex programmable logic device

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Hysteresis Based Quasi Fixed Frequency Current Control of Single Phase Full Bridge Grid Integrated Voltage Source Inverter

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ENERGIES 2022年第21期15卷 8112页

作者： Syamala, Lakshmi Sankar, Deepa Makkar, Suhara Ekkarakkudy Jos, Bos Mathew Kallarackal, Mathew Mar Athanasius Coll Engn Dept Elect & Commun Engn Kothamangalam 686666 India Adi Shankara Inst Engn & Technol Dept Elect & Elect Engn Kalady 683574 India Govt Engn Coll Dept Elect Engn Trichur 680009 India Mar Athanasius Coll Engn Dept Elect & Elect Engn Kothamangalam 686666 India

The traditional Fixed Band Hysteresis Current Control (FB-HCC) though being widely used for the current control of grid integrated voltage source inverter (GI-VSI), has the drawback of variable switching frequency. To overcome this drawback, complex programmable logic device (CPLD) based switching scheme is proposed in this paper. The proposed method calls for a single reference wave and the control concept is to terminate the rising and falling inductor current (i(L)) either by the comparator or by the CPLD, based on the nature of its slope. Termination of the i(L) with steeper slope by the comparator ensures lower current ripple, whereas the CPLD ensures constant switching frequency (f(sw)). However, the i(L) obtained with the proposed logic has a DC offset, which is corrected by modifying the reference. The basic concept, switching logic, and reference correction are thoroughly detailed. MATLAB/Simulink results are included to verify the proposed concept. The constant frequency operation of the proposed method is also validated in a 2 kW, 230 V, 50 Hz GI-VSI prototype.

关键词： complex programmable logic device constant switching frequency hysteresis current control grid integrated voltage source inverter

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A Review on HT Attacks in PLD and ASIC Designs with Potential Defence Solutions

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IETE TECHNICAL REVIEW 2018年第1期35卷 64-77页

作者： Sumathi, G. Srivani, L. Murthy, D. Thirugnana Madhusoodanan, K. Murty, S. A. V. Satya Indira Gandhi Ctr Atom Res Homi Bhabha Natl Inst Kalpakkam Tamil Nadu India Indira Gandhi Ctr Atom Res EID Embedded Syst Sect Kalpakkam Tamil Nadu India Indira Gandhi Ctr Atom Res EID Kalpakkam Tamil Nadu India Indira Gandhi Ctr Atom Res Kalpakkam Tamil Nadu India

The tremendous advancement in very large scale integration technology encourages chip designers to rely on commercial electronic design automation tools, offshore fabrication services, and outsourced intellectual property cores. As third-party involvement are more in chip design cycle, integrated circuits (IC) such as programmable logic devices (PLD) and application specific ICs (ASIC) are highly vulnerable to hardware Trojan (HT) attacks. HTs are malicious additions or modifications to existing circuit elements, which can be inserted at any stages of IC life cycle to modify/destroy the functionality, reduce reliability, leak sensitive information, etc. Besides, HT can be designed either as always on or triggered only under certain operating conditions. For example, HT attacks in safety critical applications such as nuclear power plant, space and defence will jeopardise the safety and security of the unit and cause serious consequences. Hence, it is most important to ensure that the chip being in use performs only the intended function. In this paper, an in-depth analysis of feasible HT attacks in PLD and ASIC life cycles are presented. Based on the extensive literature survey on HTs and their countermeasure techniques, the state of the art HT prevention, detection, and diagnosis techniques are recommended to the valid stages of PLD and ASIC life cycles. Therefore, incorporating possible HT defence solutions in respective phases of PLD/ASIC-based safety systems thwart them against HT attacks.

关键词： Application-specific integrated circuit complex programmable logic device Field programmable gate array Hardware Trojan Hardware Trojan detection programmable logic device

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Integrated Alarm Annunciation System with Dual Communication Capability and Operator Assisted Messaging for Nuclear Power Plant Applications

Integrated Alarm Annunciation System with Dual Communication...

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SAI Computing Conference (SAI)

作者： Shukla, Shashwat Venkatesan, Adhivaraganatham Venkatesan, Nithya Dheenadhayalan, R. Monica, Reena VIT Univ Sch Elect Engn SELECT Chennai Tamil Nadu India IGCAR Instrumentat & Control Div Chennai Tamil Nadu India VIT Univ Sch Elect Engn SENSE Chennai Tamil Nadu India

ISBN: (纸本)9781467384605

Integrated Alarm Annunciation System (AAS) in a Nuclear Power Plant (NPP) is an electronic unit which receives alarm signals from various plant control systems, receives operator inputs and controls the windows as per a standard alarm sequence. The AAS is located in the control room. In Fast Breeder Reactor (FBR), AAS receives alarm signals from plant control systems in the form of potential free digital input contacts. Important safety systems directly issue potential free contact signals to the AAS. However, less significant systems raise alarms in the form of Ethernet packets and are converted into digital signals using a separate Alarm Generation System (AGS). This segregation is used, to maintain high reliability of important systems as well as to reduce cabling in the case of less significant systems. The important aspect in the design is that any failure in the module receiving Ethernet packets has no affect on the module which receives the potential free contacts. The AAS is CPLD based. The system also has additional features like driving text to LCD/LED screens for operator information along with the Alarm log window. The AGS also have a built in self testing (BIST) feature to periodically test the healthiness of the system and indications for failures. The significance of this system focuses entirely on FBR control rooms. This paper discusses the real time implementation of the above mentioned AAS for the NPP using CPLD.

关键词： Alarm Annunciation System Nuclear Power Plant Fast Breeder Reactor Alarm Generation System complex programmable logic device Liquid Crystal Display Light Emitting Diode and Built in Self Testing

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Loose Synchronization Method for Low-power Superregenerative Wake-up Receiver 9

Loose Synchronization Method for Low-power Superregenerative...

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2015 9th International Symposium on Medical Information and Communication Technology (ISMICT)

作者： Petajajarvi, Juha Mikhaylov, Konstantin Karvonen, Heikki Vuohtoniemi, Risto Hamalainen, Matti Univ Oulu Dept Commun Engn Ctr Wireless Commun SF-90100 Oulu Finland

ISBN: (纸本)9781479980727

The use of wake-up receivers (WURs) in wireless body area networks (WBAN) has remarkable potential to improve energy efficiency. During the recent years, multiple WUR designs and architectures have been therefore proposed for WBANs and wireless sensor networks (WSN). Superregenerative oscillator (SRO) based architecture is inherently sensitive, which makes it an attractive choice for a WUR. It is known that to improve the selectivity and to reduce the energy consumption the quench frequency should be the same or in the order of data rate. Therefore, synchronization is required. To achieve this with low-power consumption, pulse width modulation is used to encode transferred address information. The decoder measures the pulse widths and uses uncertainty interval that enables loose synchronization between the transmitter and the receiver. The decoder is implemented and its power consumption is measured. Decoder operation is verified with simulations using the hardware description language simulator.

关键词： complex programmable logic device pulse width modulation WBAN

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Implement An Indoor Low Frequency Noise Reduction System Based on FXLMS Algorithm

Implement An Indoor Low Frequency Noise Reduction System Bas...

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International Forum on Computers, Electronics and Mechatronics (IFCEM)

作者： Wu Bin Ma Ji Tao Wu Pin Yunnan Acad Sci & Tech Informat Dept Network Management Ctr Kunming Peoples R China

ISBN: (纸本)9783038352907

In order to solve the hazards of indoor low-frequency noise on the human body, the low-frequency noise reduction system is designed for a confined space by using the active control theory, and the process of adaptive noise elimination is achieved through the FX-LMS algorithm. The system hardware is integrated with the sound sensor, the complex programmable logic devices, the digital to analog converter and micro control unit to build the core circuit. Furthermore, the processing software of noise reduction is implemented by the FXLMS. Through the system test, the result shows that the noise reduction system can effectively reduce the low frequency noise intensity in the confined space.

关键词： active noise control micro control unit complex programmable logic device analog to digital converter digital to analog converter

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Complete Development Platform for Multi-Level Converters and complex Control Algorithms 16

Complete Development Platform for Multi-Level Converters and...

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16th International Conference on Mechatronics (Mechatronika)

作者： Kosan, Tomas Jara, Martin Janik, Dusan Peroutka, Zdenek Univ W Bohemia Fac Elect Engn Reg Innovat Ctr Elect Engn RICE Univ 26 Plzen 30614 Czech Republic

ISBN: (纸本)9788021448179

This paper describes the modular development control platform including dedicated supporting tools. The platform was specially designed for the multi-level converters control therefore it provides up to 48 (plus 24 optional) of PWM outputs thanks to additional FPGA utilization. The combination of DSP enabled microcontroller and the FPGA allowed us to split the computational tasks between these parts which significantly helps with highly complex algorithms implementation. Fast application development is supported thanks to the software drivers covering broad range of elemental functions including communication, DMA transfers, AD service routines and basic user interface. Also an enhanced set of FPGA entities featuring various modulator functionalities are provided. Dedicated tools involves fully insulated JTAG interface with developed software allowing the platform to be programmed by a single JTAG emulator. An application example based on four level FLC converter is presented.

关键词： multi-level converter Field programmable Gate Array FPGA complex programmable logic device CPLD memory mapped devices

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Design of H-bridge Based Converter Module Used in Cascaded DSTATCOM

Design of H-bridge Based Converter Module Used in Cascaded D...

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29th Annual IEEE Applied Power Electronics Conference and Exposition (APEC)

作者： Yang, Kun Wang, Yue Yang, Hua Tao, Haijun Chen, Guozhu Zhejiang Univ Coll Elect Engn Hangzhou 310003 Zhejiang Peoples R China STSAIL Sci Technol Co LTD Dept Res & Dev Huzhou Peoples R China

ISBN: (纸本)9781479923250

The fundamental building block of cascaded static synchronous compensator used in distribution grid is H-bridge based converter module. In this paper a type of "plug and play" module was introduced to improve the device compensation performance and reliability. The module based on IGBT parallel connection was discussed about the design of electrical parameters and physical structure. In order to improve the module flexibility and anti-interference a universal module controller integrates with functions of control, communication, DC voltage sampling, fault detection and module protection was developed on complex programmable logic device. Dedicated driver cores were applied to improve the stability of HCM. Module function and stability are verified by experiment carried out on HCM experimental platform and industrial prototype.

关键词： bridge circuits design engineering fault diagnosis insulated gate bipolar transistors power convertors power distribution reliability power grids power system stability programmable logic devices static VAr compensators DC voltage sampling H-bridge based converter module design HCM stability improvement IGBT parallel connection anti interference improvement cascaded DSTATCOM cascaded static synchronous compensator complex programmable logic device device compensation performance improvement device reliability improvement distribution grid electrical parameter design fault detection module flexibility improvement module protection physical structure design plug-and-play module universal module controller Capacitors Control systems Insulated gate bipolar transistors Power system reliability Prototypes Reliability Voltage control

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Energy-Efficient Light Driver Controller Using complex programmable logic

Energy-Efficient Light Driver Controller Using Complex Progr...

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IEEE Conference on Systems, Process and Control (ICSPC)

作者： Dollah, Abdul Muiz Al Junid, Syed Abdul Mutalib Othman, Zulkifli Osman, Fairul Nazmie Shariff, Khairul Khaizi Mohd Univ Teknol MARA Fac Elect Engn Shah Alam Selangor Malaysia

ISBN: (纸本)9781479922086

In pursuit of energy-efficient technology, lighting system has been one of the major concerns of global warming because of high power consumption. Therefore, this study attempted to investigate and design a new mechanism for reducing energy consumption by targeting the indoor lighting system. This study has been carried out in three stages: design, simulation, and implementation. The complex programmable logic device (CPLD) Altera Max EPM7128SLC84-15N has been used as a target device for controlling the luminance and power consumption of LED at the design stage. Several ranges of duty cycle starting from 6% to 93% have been designed, simulated, and tested on CPLD to determine the suitable luminance range at the optimal power consumption for indoor lighting. Altera Quartus II version 11.1 has been used to construct, compile, and simulate the proposed design. Meanwhile, Arduino Uno R3 has been used as an interface for the sensor at the implementation stage. The system has been successfully developed and tested using several ranges of input variables. Evidently, the optimal luminance is influenced by the range of duty cycle and the numbers of the LED bulb. Hence, the proposed system using 15 LEDs at 73% duty cycle produces 480 lx, which approaches the normal office illumination at 500 lx. Therefore, the proposed system is capable of reducing 27% power consumption to produce optimal standard indoor illumination.

关键词： complex programmable logic device energy efficiency chip current driver

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The Design of Switched Reluctance Motor Drive System Based on Single Chip Microcontroller and CPLD

The Design of Switched Reluctance Motor Drive System Based o...

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International Conference on Information Technology and Management Innovation (ICITMI2012)

作者： Wang, Chenning Chenz, Shijun Zha, Changli Anqing Normal Coll Sch Phys & Elect Engn Anqing Anhui Peoples R China

ISBN: (纸本)9783037855744

A three-phase 12/8 pole switched reluctance motor drive system is introduced based on single chip microcontroller STC12LE5410AD and CPLD EPM240T100C5N. The design details of the controller are described in this application .To solve the nonlinear problem of switched reluctance motor, PI control algorithms are used to achieve the motor current control loop and speed control loop. The experimental results show that the hardware and software design of switched reluctance motor drive system are reasonable, and the proposed dual closed-loop control method is correct and feasible.

关键词： Switched Reluctance Motor Single Chip Microcontroller complex programmable logic device Speed Control System

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