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16th International Conference Mixed Design of Integrated Circuits and Systems

作者： Barkalov, Alexander Titarenko, Larysa Bieganowski, Jacek Univ Zielona Gora Inst Comp Engn & Elect PL-65246 Zielona Gora Poland

ISBN: (纸本)9788392875604

The paper presents new research results of synthesis of compositional microprogram control unit with extended microinstruction format. The method is addressed for programmable logic devices such as CPLD and FPGA and it is oriented on reduction of hardware amount of CMCU addressing circuit. The reduction is reached due to decrease of the number of terms in system of Boolean functions describing the addressing circuit. The research results shows that application of the method for tested GSAs gives on average 50% decrease of hardware amount and 30% decrease of cycle time when compared to CMCU base structure.

关键词： compositional microprogram control unit CMCU CPLD FPGA

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Optimization of the circuit of compositional microprogram control unit with mutual memory

Optimization of the circuit of compositional microprogram co...

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9th International Conference on the Experience of Designing and Application of CAD Systems in Microelectronics

作者： Barkalov, A. A. Titarenko, L. Wisniewski, R. Univ Zielona Gora Inst Comp Engn & Elect Ul Podgorna 50 PL-65246 Gora Poland Donetsk Natl Tech Univ Pokrovsk Ukraine

The method of optimal addressing of microinstructions of CMCU with mutual memory is proposed. The method is based on the effective encoding of classes of the pseudo-equivalent operational linear chains. An example of ... 详细信息

ISBN: (纸本)9789665335870

关键词： circuits programmable logic devices compositional microprogram control unit

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Analysis of Resource Utilization in compositional microprogram control unit with Elementary Operational Linear Chains

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IFAC Proceedings Volumes 2009年第21期42卷 205-208页

作者： Małgorzata Kołopieńczyk Larysa Titarenko University of Zielona Góra Instytute of Computer Engineering and Electronics Podgórna 50 65–246 Zielona Góra POLAND

This paper presents results of decreasing hardware resources usage for compositional microprogram control units with code sharing and elementary operational linear chains. Two types of microprogram control units are compared: a structure with address converter and without it. For synthesis and implementation of the microprogram control unit Xilinx ISE 8.2i package was used. Four optimization strategies available in the ISE package have been applied. The test results show that for some examples memory consumption drops even by 50% in comparison to the implementation without the address converter. It's important to notice that adding an additional block (address converter) to the microprogram control unit does not cause an increase in hardware resource use.

关键词： compositional microprogram control unit elementary operational linear chains address converter FPGA VHDL

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CODE CONVERSION IN compositional microprogram control unitS

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CYBERNETICS AND SYSTEMS ANALYSIS 2011年第5期47卷 763-772页

作者： Barkalov, A. A. Titarenko, L. A. Donetsk Natl Tech Univ Donetsk Ukraine Univ Zielona Gora Zielona Gora Poland Kharkov Natl Univ Radioelectron Kharkov Ukraine

The joint use of structural decomposition and code conversion is proposed. The method is oriented to reducing the hardware in compositional microprogram control units. This reduction is due to the decrease in the number of arguments for irregular functions and in the number of the functions themseves. Embedded memory blocks are used to implement regular functions. Design methods and an example are discussed. Experimental results are given.

关键词： compositional microprogram control unit FPLD structural decomposition optimization

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OPTIMIZATION OF CIRCUITS OF compositional microprogram control unitS IMPLEMENTED ON FPGA

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CYBERNETICS AND SYSTEMS ANALYSIS 2011年第1期47卷 166-174页

作者： Barkalov, A. A. Titarenko, L. A. Efimenko, K. N. Univ Zielona Gora Zielona Gora Poland Donetsk Natl Tech Univ Donetsk Ukraine

Two methods are proposed for microinstruction addressing in interpreting a control algorithm by a compositional microprogram control unit (CMCU). The method of refined addressing allows one to uniquely identify outputs of operational linear chains (OLCs) using a minimal number of address bits. The method of optimal addressing makes it possible to represent classes of pseudoequivalent OLCs using a minimal number of generalized intervals of the code space. The proposed methods are illustrated by examples. Both methods make it possible to reduce the number of look-up table (LUT) elements in a CMCU logic circuit in comparison with its base structure. In the majority of cases, the clock period decreases with decreasing the amount of hardware.

关键词： compositional microprogram control unit EPLD optimization microinstruction addressing

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Synthesis of compositional microprogram control units with sharing codes and address decoder

Synthesis of compositional microprogram control units with s...

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International Conference on Mixed Design of Integrated Circuits and Systems

作者： Wisniewski, R. Barkalov, A. A. Titarenko, L. University of Zlelona Góra Poland Institute of Computer Engineering and Electronics University of Zielona Góra Poland

ISBN: (纸本)8392263219

The method of synthesis of compositional microprogram control units with sharing codes and address decoder is proposed. In comparison with traditional way of synthesis of control units with sharing codes, there is additional block (Address Decoder) implemented. Thanks to it proposed method permits to use the principle of sharing codes under any characteristics of operational linear chains of initial flow-chart.

关键词： control unit compositional microprogram control unit Operational Linear Chains Sharing Codes

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DESIGN OF compositional microprogram control unitS WITH ELEMENTARY OPERATIONAL LINEAR CHAINS

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IFAC Proceedings Volumes 2006年第17期39卷 191-194页

作者： Remigiusz Wiśniewski University of Zielona Góra Faculty of Electrical Engineering Computer Science and Telecommunications Institute of Computer Engineering and Electronics ul. Podgórna 50 65-246 Zielona Góra Poland

A method of designing of compositional microprogram control units with Elementary Operational Linear Chains is proposed. The method is based on the special encoding of the Operational Linear Chains. Such an approach permits to decrease the number of logic blocks of the destination FPGA device. An exemplary application of the proposed method is discussed. The investigations conducted by the author have shown that the proposed method permits to decrease the usage of the logic blocks of destination device up to 20%.

关键词： compositional microprogram control unit Elementary Operational Linear Chain Logic Devices Field Programmable Gate Arrays

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Optimization of CMCU with Code Sharing

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CYBERNETICS AND SYSTEMS ANALYSIS 2021年第5期57卷 685-697页

作者： Barkalov, A. A. Titarenko, L. A. Baiev, A. V. Matviienko, A. V. Univ Zielona GOra Zielona Gora Poland Vasyl Stus Donetsk Natl Univ Vinnytsia Ukraine Univ Zielona Gora Zielona Gora Poland Kharkiv Natl Univ Radio Elect Kharkiv Ukraine Vasyl Stus Donetsk Natl Univ Vinnytsia Ukraine Peoly LLC Vinnytsia Ukraine Natl Acad Sci Ukraine VM Glushkov Inst Cybernet Kiev Ukraine

The article proposes a method for reducing the number of LUT elements in the circuit of a compositional microprogram control unit (CMCU) with code sharing. The method is based on the two-fold encoding of operator linear chains (OLC). Each chain has a code as an element of the OLC set and as a class element of this set. This approach allows obtaining a two-level microinstruction addressing unit. The control memory of the CMCU is implemented in the embedded memory blocks. The article considers an example of synthesis and provides an analysis of the proposed method.

关键词： compositional microprogram control unit LUT EMB code sharing

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REDUCTION OF HARDWARE EXPENSES IN control unit WITH CODE SHARING

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CYBERNETICS AND SYSTEMS ANALYSIS 2013年第3期49卷 424-433页

作者： Barkalov, O. O. Titarenko, L. A. Lavrik, A. S. Donetsk Natl Tech Univ Donetsk Ukraine Uniwersytet Zielonogorski Zielona Gora Poland Kharkov Natl Univ Radio Elect Kharkov Ukraine

A method for reducing hardware expenses in compositional microprogram control unit and CPLD chips is proposed. This method is based on the use of pseudoequivalent operational linear chains, wide fan-in of PAL macrocells, and existence of free outputs of embedded memory block in CPLD chips. An example of applying the method is given. It is shown that the method reduces hardware expenses to 30%.

关键词： flowchart of algorithm control unit compositional microprogram control unit code sharing programmable logic devices of CPLD type addressing of microcommands

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NEW MEANS OF CYBERNETICS, INFORMATICS, COMPUTER ENGINEERING, AND SYSTEMS ANALYSIS MODIFICATION OF THE MICROCOMMAND ADDRESSING SYSTEM IN A control unit WITH CODE SHARING

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CYBERNETICS AND SYSTEMS ANALYSIS 2013年第1期49卷 139-148页

作者： Barkalov, A. A. Titarenko, L. A. Miroshkin, A. N. Univers Zielona Gora Zielona Gora Poland Donetsk Natl Tech Univ Donetsk Ukraine

This article proposes two modifications of the microcommand addressing system in a compositional microprogram control unit with code sharing. The modifications are based on using FSM pseudoequivalent states to reduce the number of rows in the FSM transition table and thereby to reduce the complexity of the combinational part of the device. Methods are proposed for synthesizing compositional control units with a modified microcommand addressing system. The research results are presented and appropriate fields of application of the methods proposed are considered.

关键词： graph-scheme of an algorithm control unit compositional microprogram control unit code sharing FPGA programmable logic microcommand addressing

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