检索结果-内蒙古大学图书馆

An Exact Approach for GPC-Based compressor tree Synthesis

IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES 2013年第12期E96A卷 2553-2560页

作者： Matsunaga, Taeko Kimura, Shinji Matsunaga, Yusuke Kyushu Sangyo Univ Fac Engn Dept Elect Engn & Informat Technol Fukuoka 8138503 Japan Waseda Univ Grad Sch Informat Prod & Syst Kitakyushu Fukuoka 8080135 Japan Kyushu Univ Dept Adv Informat Technol Fac Informat Sci & Elect Engn Fukuoka 8190395 Japan

Multi-operand adders that calculate the summation of more than two operands usually consist of compressor trees, which reduce the number of operands to two without any carry propagation, and carry-propagate adders for the two operands in the ASIC implementation. compressor trees that consist of full adders and half adders cannot be implemented efficiently on LUT-based FPGAs, and carry-chains or dedicated structures have been utilized to produce multi-operand adders on FPGAs. Recent studies indicate that compressor trees can be implemented efficiently on LUTs using Generalized Parallel Counters (GPCs) as the building blocks of compressor trees. This paper addresses the problem of synthesizing compressor trees based on GPCs. Based on the observation that characteristics such as the area, power, and delay correlate roughly to the total number and the maximum level of GPCs, the target problem can be regarded as a minimization problem for the total number of GPCs and the maximum levels of the GPCs, for which an ILP-based approach is proposed. The key point of our formulation is not to model the problem based on the structures of compressor trees like the existing approach, but instead the compression process itself is used to reduce the number of variables and constraints in the ILP formulation. The experimental results demonstrate the advantage of our formulation in terms of the quality and runtime.

关键词： compressor tree generalized parallel counter integer linear programming arithmetic synthesis

来源：评论

学校读者我要写书评

暂无评论

Advanced compressor tree Synthesis for FPGAs

引用

IEEE TRANSACTIONS ON COMPUTERS 2018年第8期67卷 1078-1091页

作者： Kumm, Martin Kappauf, Johannes Univ Kassel Digital Technol Grp D-34125 Kassel Germany

This work presents novel methods for the optimization of compressor trees for FPGAs as required in many arithmetic computations. As demonstrated in recent work, important key elements for the design of efficient but fast compressor trees are target-optimized 4:2 compressors as well as generalized parallel counters (GPCs). However, the optimization of a compressor tree for minimal resources using both compressors and GPCs has not been addressed so far. As this combined optimization is a non-trivial task, three methods are proposed to find best solutions for a given problem size: 1) a heuristic that obtains compressor trees with typically less resources and fewer stages than state-of-the-art heuristics, 2) an integer linear programming (ILP)-based methodology that finds optimal compressor trees using the fewest stages possible, 3) a combined approach that partially solves the problem heuristically to reduce the search space for the I LP-based method. In all methods, the cost for pipeline registers can be included Synthesis experiments show that the proposed methods provide pipelined compressor trees with about 40 percent less LUTs compared to trees of 2-input adders at the cost of being about 12...20 percent slower.

关键词： Digital arithmetic compressor tree FPGA optimization

来源：评论

学校读者我要写书评

暂无评论

OPACT: Optimization of Approximate compressor tree for Approximate Multiplier

OPACT: Optimization of Approximate Compressor Tree for Appro...

引用

25th Design, Automation and Test in Europe Conference and Exhibition (DATE)

作者： Xiao, Weihua Zhuo, Chcng Qian, Weikang Shanghai Jiao Tong Univ Univ Michigan Shanghai Jiao Tong Univ Joint Inst Shanghai Peoples R China Zhejiang Univ Coll Informat Sci & Elect Engn Hangzhou Zhejiang Peoples R China Shanghai Jiao Tong Univ MoE Key Lab Artificial Intelligence Shanghai Peoples R China

ISBN: (纸本)9783981926361

Approximate multipliers have attracted significant attention of researchers for designing low-power systems. The most area-consuming part of a multiplier is its compressor tree (CT). Hence, the prior works proposed various approximate compressors to reduce the area of the CT. However, the compression strategy for the approximate compressors has not been systematically studied: Most of the prior works apply their ad hoc strategies to arrange approximate compressors. In this work, we propose OPACT, a method for optimizing approximate compressor tree for approximate multiplier. An integer linear programming problem is first formulated to co-optimize CT's area and error. Moreover, since different connection orders of the approximate compressors can affect the error of an approximate multiplier, we formulate another mixed-integer programming problem for optimizing the connection order. The experimental results showed that OPACT can produce approximate multipliers with an average reduction of 24.4% and 8.4% in power-delay product and mean error distance, respectively, compared to the best existing designs with the same types of approximate compressors used.

关键词： Approximate Multipliers compressor tree Approximate compressors Integer Programming Optimization

来源：评论

学校读者我要写书评

暂无评论

compressor tree Synthesis on Commercial High-Performance FPGAs

引用

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2011年第4期4卷 39-39页

作者： Parandeh-Afshar, Hadi Neogy, Arkosnato Brisk, Philip Ienne, Paolo Ecole Polytech Fed Lausanne Lausanne Switzerland Univ Calif Riverside Riverside CA 92521 USA Indian Inst Technol Kharagpur 721302 W Bengal India

compressor trees are a class of circuits that generalizes multioperand addition and the partial product reduction trees of parallel multipliers using carry-save arithmetic. compressor trees naturally occur in many DSP applications, such as FIR filters, and, in the more general case, their use can be maximized through the application of high-level transformations to arithmetically intensive data flow graphs. Due to the presence of carry-chains, it has long been thought that trees of 2- or 3-input carry-propagate adders are more efficient than compressor trees for FPGA synthesis;however, this is not the case. This article presents a heuristic for FPGA synthesis of compressor trees that outperforms adder trees and exploits carry-chains when possible. The experimental results show that, on average, the use of compressor trees can reduce critical path delay by 33% and 45% respectively, compared to adder trees synthesized on the Xilinx Virtex-5 and Altera Stratix III FPGAs.

关键词： Algorithms Performance Field Programamble Gate Array (FPGA) look-up table (LUT) carry chain compressor tree

来源：评论

学校读者我要写书评

暂无评论

OPACT: optimization of approximate compressor tree for approximate multiplier 22

OPACT: optimization of approximate compressor tree for appro...

引用

Proceedings of the 2022 Conference & Exhibition on Design, Automation & Test in Europe

作者： Weihua Xiao Cheng Zhuo Weikang Qian Shanghai Jiao Tong University China Zhejiang University China Shanghai Jiao Tong University China and Shanghai Jiao Tong University China

ISBN: (纸本)9783981926361

关键词： approximate multipliers integer programming approximate compressors compressor tree optimization

来源：评论

学校读者我要写书评

暂无评论

High-efficiency compressor trees for Latest AMD FPGAs

引用

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2024年第2期17卷 1-32页

作者： Hossfeld, Konstantin J. Damsgaard, Hans Jakob Nurmi, Jari Blott, Michaela Preusser, Thomas B. Regus Altmarkt AMD Altmarkt 10 b-d D-01067 Dresden Germany Tampere Univ Tampere Finland Tampere Univ Fac Informat Technol & Commun Sci Korkeakoulunkatu 1 Tampere 33720 Finland AMD 2020 Bianconi AveCitywest Campus Dublin D24 T683 Ireland

High-fan-in dot product computations are ubiquitous in highly relevant application domains, such as signal processing and machine learning. Particularly, the diverse set of data formats used in machine learning poses a challenge for flexible efficient design solutions. Ideally, a dot product summation is composed from a carry-free compressor tree followed by a terminal carry-propagate addition. On FPGA, these compressor trees are constructed from generalized parallel counters whose architecture is closely tied to the underlying reconfigurable fabric. This work reviews known counter designs and proposes new ones in the context of the new AMD VersalT fabric. On this basis, we develop a compressor generator featuring variable-sized counters, novel counter composition heuristics, explicit clustering strategies, and case-specific optimizations like logic gate absorption. In comparison to the VivadoT default implementation, the combination of such a compressor with a novel, highly efficient quaternary adder reduces the LUT footprint across different bit matrix input shapes by 45% for a plain summation and by 46% for a terminal accumulation at a slight cost in critical path delay still allowing an operation well above 500 MHz. We demonstrate the aptness of our solution at examples of low-precision integer dot product accumulation units.

关键词： compressor tree matrix compression parallel counters

来源：评论

学校读者我要写书评

暂无评论

Area Optimized Synthesis of compressor trees on Xilinx FPGAs Using Generalized Parallel Counters

引用

IEEE ACCESS 2019年 7卷 134815-134827页

作者： Yuan, Yuelai Tu, Le Huang, Kan Zhang, Xiaoqiang Zhang, Tiejun Chen, Dihu Wang, Zixin Sun Yat Sen Univ Sch Elect & Informat Technol Guangzhou 510006 Peoples R China Sun Yat Sen Univ Xinhua Coll Guangzhou 510520 Peoples R China

Early compressor trees based on carry-save adders and single-column parallel counters show good performance in ASIC design, but do not adapt well to modern field-programmable gate arrays (FPGAs). Recently, compressor trees built from generalized parallel counters (GPCs) were synthesized on FPGAs to address this issue. Despite the improved timing performance of GPC-based compressor trees, area reduction is not as significant as delay, and can be further optimized. In this paper, we propose improved GPC mappings as well as new approaches for GPC cascading and binding for Xilinx FPGAs. With these improvements, we develop an integer linear programming (ILP) method for FPGA synthesis of GPC-based compressor trees that supports cascading and binding between GPCs. Experimental results show that the single-cycle compressor trees produced by the proposed ILP can reduce the average area by 42.40% compared with those generated by existing heuristic method, but are 13.16% slower;the pipelined compressor trees produced by the proposed ILP can reduce the average area by 33.43% at the cost of an average 14.35% decrease in maximum clock frequency compared with those obtained by existing heuristic method.

关键词： Generalized parallel counter (GPC) compressor tree integer linear programming (ILP) field programmable gate array (FPGA)

来源：评论

学校读者我要写书评

暂无评论

Field Programmable compressor trees: Acceleration of Multi-Input Addition on FPGAs

引用

ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS 2009年第2期2卷 13-13页

作者： Cevrero, Alessandro Athanasopoulos, Panagiotis Parandeh-Afshar, Hadi Verma, Ajay K. Attarzadeh-Niaki, Seyed-Hosein Nicopoulos, Chrysostomos Gurkaynak, Frank K. Brisk, Philip Leblebici, Yusuf Ienne, Paolo Ecole Polytech Fed Lausanne Lausanne Switzerland Univ Cyprus Nicosia Cyprus Royal Inst Technol Stockholm Sweden Zunich ETHZ Swiss Fed Inst Technol Zunich Switzerland

Multi-input addition occurs in a variety of arithmetically intensive signal processing applications. The DSP blocks embedded in high-performance FPGAs perform fixed bitwidth parallel multiplication and Multiply-ACcumulate (MAC) operations. In theory, the compressor trees contained within the multipliers could implement multi-input addition;however, they are not exposed to the programmer. To improve FPGA performance for these applications, this article introduces the Field Programmable compressor tree (FPCT) as an alternative to the DSP blocks. By providing just a compressor tree, the FPCT can perform multi-input addition along with parallel multiplication and MAC in conjunction with a small amount of FPGA general logic. Furthermore, the user can configure the FPCT to precisely match the bitwidths of the operands being summed. Although an FPCT cannot beat the performance of a well-designed ASIC compressor tree of fixed bitwidth, for example, 9x9 and 18x18-bit multipliers/MACs in DSP blocks, its configurable bitwidth and ability to perform multi-input addition is ideal for reconfigurable devices that are used across a variety of applications.

关键词： Algorithms Performance Field Programmable Gate Array (FPGA) compressor tree Field Programmable compressor tree (FPCT)

来源：评论

学校读者我要写书评

暂无评论

Towards Globally Optimal Design of Multipliers for FPGAs

引用

IEEE TRANSACTIONS ON COMPUTERS 2023年第5期72卷 1261-1273页

作者： Bottcher, Andreas Kumm, Martin Fulda Univ Appl Sci Appl Comp Sci Dept D-36037 Fulda Germany

The design of a multiplier typically consists of three steps: (1) partial product generation, (2) compressor tree design and (3) the selection of the final adder. Conventionally, these three steps are performed consecutively. However, when targeting FPGAs, there are many possibilities in all three design steps that heavily influence each other. This proposal presents for the first time a holistic optimization, combining all three optimization steps yielding a minimum amount of look-up-tables (LUTs) while it can also guarantee the minimal number of (pipeline) stages. An ILP-formulation for the determination of a combined, globally optimal solution for the multiplier tiling, compressor tree generation and final adder selection is proposed. With globally optimal we mean that the best solution is found for a given set of sub-multipliers for partial product generation, compressors and final *** allows to improve the quality and evaluate the limitations of existing heuristic 3-step approaches. It is shown experimentally for the example of Xilinx FPGAs, that globally optimal solutions can be obtained for multiplier sizes of practical relevance, leading to significant LUT reductions. Additional packing density experiments show that a significantly larger number of multiplier instances can be mapped to the same device.

关键词： Adders Field programmable gate arrays Costs Table lookup Optimization Shape Proposals compressor tree computer arithmetic FPGA integer linear programming multiplier multiplier tiling

来源：评论

学校读者我要写书评

暂无评论

Resource Optimal Squarers for FPGAs 32

Resource Optimal Squarers for FPGAs

引用

32nd International Conference on Field-Programmable Logic and Applications (FPL)

作者： Boettcher, Andreas Kumm, Martin de Dinechin, Florent Fulda Univ Appl Sci Fulda Germany Univ Lyon INSA Lyon INRIA CITI Lyon France

ISBN: (纸本)9781665473903

Squaring is an essential operation in computer arithmetic that can be considered as a special case of multiplication where several simplifications can be applied to reduce the complexity of the resulting circuit. However, the design of a squarer is not straightforward for modern FPGAs that provide embedded DSP blocks and look-up-tables (LUTs). This work proposes a flexible method to design resource optimal squarers, i.e., a squarer that uses a minimum number of LUTs for a user-defined number of DSP blocks. The method uses an integer linear programming (ILP) formulation based on a generalization of multiplier tiling. It is shown that the proposed squarer design method significantly improves the LUT utilization for a given number of DSPs over previous methods, while maintaining a similar critical path delay and latency.

关键词： squarer multiplier tiling compressor tree integer linear programming computer arithmetic

来源：评论

学校读者我要写书评

暂无评论

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案：

请选择收藏分类：

通借通还

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：