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computer architectures FOR IMAGE-PROCESSING IN THE USA

SIGNAL PROCESSING 1981年第3期3卷 217-230页

作者： REEVES, AP School of Electrical Engineering Purdue University West Lafayette IN 47907 USA

Innovative computer architectures have been developed to meet the high speed computation needs of image processing applications. These architectures take advantage of the highly structured characteristics of image data and image processing algorithms. In this paper several alternative architectures for image processing are discussed and some current hardware development projects in the USA are described. Two established computer architectures for image processing are highly parallel binary array processing and pipeline processing. Current designs involving these architectures make good use of Large Scale Integration technology. New emerging architectures, which are still in the development stage, include multi-microprocessor systems and analog processors based on charge coupled devices. Zusammenfassung Neurtige Konzeptionen der Rechnerarchitektur wurden entwickelt, um den Anforderungen zu genügen, die die Bildverarbeitung hinsichtlich der Rechengeschwindigkeit stellt. In diesem Artikel werden einige Konzepte zur Rechnerarchitektur in der Bildverarbeitung diskutiert; einige laufende Hardware-Entwicklungsprojekte in den USA werden beschrieben. Zwei etablierte Architekturkonzepte für die Bildverarbeitung sind: die weitgehend parallele binäre Verarbeitung von Feldern (Array Processing) und die Verarbeitung nach dem Pipelining-Prinzip. Beim Entwurf von Spezialrechnern mit diesen Konzepten lassen sich hochintegrierte Schaltungen gut einsetzen. Neuere Konzepte zur Rechnerarchitektur sind noch im Entwicklungsstadium: unter ihnen befinden sich Multi-Mikroprozessor-systeme sowie Analogprozessoren mit Ladungstransferschaltungen.

关键词： computer architectures parallel binary array pipeline

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computer architectures and safety integrity level apportionment

Computer architectures and safety integrity level apportionm...

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9th International Conference on computer Aided Design, Manufacture and Operation in the Railway and Other Advanced Transit Systems

作者： Jansen, H Schäbe, H TUV InterTraffic GmbH Cologne Germany

ISBN: (纸本)1853127159

Currently, technical systems are becoming more and more complex. A main contribution comes from electronic, control systems that allow for a larger number of functions. The concept of Safety Integrity Levels (SILS) has been developed within different systems of standards (IEC 61508, EN 50129 / EN 50128 and DEF-STAN 00-56). These standards are applied in different areas: control technology (IEC 61508), railway technology (EN 50129 and EN 50128) and defence technology (DEF-STAN 00-56). SILs are a tool for assigning safety targets to systems. The concept of a safety SIL within different standards is explained. The problem of assigning SILS to functional units within a system is discussed, especially bow a SIL is realised by a certain safety architecture of a system. Some standards give rules for system architecture and how to achieve a higher SIL for a system designed from constituents that have a lower SIL. Examples for system architectures and SIL assignment are given. For all systems, a choice of SILs for hardware and software is discussed and the problems arising are described.

关键词： Safety Integrity Level (SIL) SIL apportionment EN 50129 fault tree analysis computer architectures railway technology DEF-STAN-00-56 IEC 61508

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computer architectures using nanotechnology

Computer architectures using nanotechnology

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作者： Sun, Yichun Lehigh University

学位级别：Ph.D.

According to the International Technology Roadmap for Semiconductors, the emerging research devices such as Resonant Tunneling Diodes/Transistors (RTD/RTT), Single Electron Transistors(SET) and Quantum Cellular Automata (QCA) are expected to start replacing the CMOS devices in many applications by the end of the next decade. Unfortunately, these new technologies cannot implement the traditional Boolean logic efficiently. On the other hand, they are well suited for threshold logic. Clearly, along with the development of the new devices, one should also explore the new design techniques that are compatible with these devices. This work focuses on the development of strategies for design and implementation of computer architectures with nanotechnology. Recent studies have demonstrated that the reliability of a nanoelectronic logic gate is dependent upon its fan-in. All the designs presented in this work therefore employ bounded fan-in threshold logic. We develop general schemes to decompose any threshold function into a network of threshold gates with bounded fan-in using a k-ary tree structure. For some applications, e.g., comparison function, the decomposition scheme leads to a circuit that has a lower complexity and higher speed. A new strategy to design adders which form the fundamental logic block of any computational unit will be discussed. This strategy allows one to design adders with required speed and complexity using threshold gates with a given fan-in bound. We show that by exploiting the properties of threshold functions, one can get new adder architectures that are much faster and far less complex than the Group Carry Look-ahead Adders (GCLA) presently employed in most modern processors. Our strategies also allow us a three-way trade-off between the hardware complexity, the reliability and the speed. Different implementation styles with nanoelectronic threshold gates will also be presented. We show that a systolic implementation of threshold logic can all

关键词： computer architectures nanotechnology threshold logic

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A HIERARCHICAL TAXONOMIC SYSTEM FOR computer architectures

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computer 1990年第3期23卷 64-74页

作者： DASGUPTA, S Center for Adv. Comput. Studies Univ. of Southwestern Louisiana Lafayette LA

A novel hierarchical architectural taxonomic system that appears to possess the desirable characteristics of a good taxonomic scheme is presented. The author focuses on the endoarchitecture, i.e. the logical structure, control and behavior of the integrated system of hardware components. The starting point for this system is D.B. Skillicorn's scheme (see ibid., vol.21, no.11, p.46-57, 1988). However, the system both extends and departs from Skillicorn's scheme, using formulas inspired by chemical notation to classify computer architectures in a way that provides both predictive power and explanatory capabilities

关键词： chemical notation classification computer architecture computer architectures endoarchitecture explanatory capabilities hardware components integrated system logical structure novel hierarchical architectural taxonomic system predictive power taxonomic scheme

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A TAXONOMY FOR computer architectures

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computer 1988年第11期21卷 46-57页

作者： SKILLICORN, DB Dept. of Comput. & Inf. Sci. Queen's Univ. Kingston Ont.

A taxonomy is presented that extends M.J. Flynn's (IEEE ***., vol. C-21, no.9, p.948-60, Sept. 1972), especially in the multiprocessor category. It is a two-level hierarchy in which the upper level classifies architectures based on the number of processors for data and for instructions and the interconnections between them. A lower level can be used to distinguish variants even more precisely; it is based on a state-machine view of processors. The author suggests why taxonomies are useful in studying architecture and shows how this applies to a number of modern architectures

关键词： computer architecture computer architectures multiprocessing systems multiprocessor state-machine

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Cyclical Processor and computer architectures for Highly Parallel Applications

Cyclical Processor and Computer Architectures for Highly Par...

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作者： Fut-Suan Wong University Of British Columbia

学位级别：博士

During the last few decades, the search for powerful computing machines has been one of the several endless pursuits among the scientific community. In this thesis, several novel architectural ideas for the designs of high- performance computing machines are presented, and the practicality and usefulness of cyclical architectures -- ones which have their hardware resources cyclically arranged -- in this respect are examined. These ideas are illustrated with the use of specific application examples including parallel sorting, packet-switched communications and the design methodology of a class of next-generation computers. In the first part of our studies, the structure and control algorithms of a single-chip, recirculating systolic sorter (RSS), are presented. The correctness of the algorithms is proved, and general operational constraints are derived. This parallel sorter is highly amenable to VLSI implementations because of the simple control structure and the regular, repetitive and near-neighbour type of interconnections required. The number of quadruple comparators needed to sort N items is N/4, and the average sorting time is found to be bounded by (logN)**2 and N. A hardware termination is incorporated into the control unit of the sorter, so that the sorting process can be terminated as soon as the input list is in the desired order. In the second part of our studies, a' novel loop~ structured switching network (LSSN) is presented. It is intended for packet communications in large-scale systems consisting of hundreds to thousands of interconnected devices. with L loops -- where L is a power of two, it can connect up to N=L(1ogL) pairs of transmitters and receivers, using only N/2 two-by~two switches; in terms of switch counts and the amounts of wiring, this network is very advantageous when the value of N is large. It can be extended incrementally, and is free of the store-and-forward type of deadlocks which prevail in other cyclical, packet-switched networks

关键词： computer architectures next-generation computing systolic arrays parallel sorting packet-switched networks store-and-forward deadlocks data-driven and control-driven computations

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Performance Modeling of Single Processor and Multi-Processor computer architectures

Performance Modeling of Single Processor and Multi-Processor...

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作者： Commissariat, Hormazd P. Virginia Tech | University

Determining the optimum computer architecture configuration for a specific application or a generic algorithm is a difficult task. The complexity involved in today’s computer architectures and systems makes it more difficult and expensive to easily and economically implement and test full functional prototypes of computer architectures. High level VHDL performance modeling of architectures is an efficient way to rapidly prototype and evaluate computer architectures. Determining the architecture configuration is fixed, one would like to know the tolerance and expected performance of individual/critical components and also what would be the best way to map the software tasks onto the processor(s). Trade-offs and engineering compromises can be analyzed and the effects of certain component failures and communication bottle-necks can be studied. A part of the research work done for the RASSP (Rapid Prototyping of Application Specific Signal Processors) project funded by Department of Defense contracts is documented in this thesis. The architectures modeled include a single-processor, single-global-bus system; a four processor, single-global-bus system; a four processor, multiple-local-bus, single-global-bus system; and finally, a four processor multiple-local-bus system interconnected by a crossbar interconnection switch. The hardware models used are mostly legacy/inherited models from an earlier project and they were upgraded, modified and customized to suit the current research needs and requirements. The software tasks that are run on the processors are pieces of the signal and image processing algorithm run on the Synthetic Aperture Radar (SAR). The communication between components/devices is achieved in the form of tokens which are record structures. The output is a trace file which tracks the passage of the tokens through various components of the architecture. The output trace file is post-processed to obtain activity plots and latency plots for individual co

关键词： Performance Modeling computer architectures VHDL Multi-Processor Thesis

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A Survey on Memory-centric computer architectures

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ACM JOURNAL ON EMERGING TECHNOLOGIES IN COMPUTING SYSTEMS 2022年第4期18卷 79-79页

作者： Gebregiorgis, Anteneh Hoang Anh Du Nguyen Yu, Jintao Bishnoi, Rajendra Taouil, Mottaqiallah Catthoor, Francky Hamdioui, Said Delft Univ Technol Mekelweg 4 NL-2628 CD Delft Netherlands Interuniv Microelect Ctr IMEC Leuven Belgium

Faster and cheaper computers have been constantly demanding technological and architectural improvements. However, current technology is suffering from three technology walls: leakage wall, reliability wall, and cost wall. Meanwhile, existing architecture performance is also saturating due to three well-known architecture walls: memory wall, power wall, and instruction-level parallelism (ILP) wall. Hence, a lot of novel technologies and architectures have been introduced and developed intensively. Our previous work has presented a comprehensive classification and broad overview of memory-centric computer architectures. In this article, we aim to discuss the most important classes of memory-centric architectures thoroughly and evaluate their advantages and disadvantages. Moreover, for each class, the article provides a comprehensive survey on memory-centric architectures available in the literature.

关键词： Computation-in-memory computer architectures resistive computing classification

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The future of computing - new architectures and new technologies - Part 2 parallelism and information

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COMPUTING & CONTROL ENGINEERING JOURNAL 2002年第3期13卷 137-142页

作者： Warren, P BTexact Technol Foresight & Scenarios Team Ipswich IP5 3RE Suffolk England

The worlds of biology and physics both provide massive parallelism that can be exploited to speed up lengthy computations-with profound consequences for both everyday computing and cryptography. This article explores these possibilities and then, drawing also on material from a previous article, sketches what developments we may expect to see in the next few decades of computing technology.

关键词： Parallel architecture cryptography new technologies computer architectures massive parallelism technological forecasting future General computer topics biology computing parallel architectures physics computing computation speed Physics and chemistry computing Biology and medical computing information Data security computing technologies natural parallelism

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MODERN architectures FOR EMBEDDED RECONFIGURABLE SYSTEMS - A SURVEY

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JOURNAL OF CIRCUITS SYSTEMS AND computerS 2009年第2期18卷 209-254页

作者： Jozwiak, Lech Nedjah, Nadia Eindhoven Univ Technol NL-5600 MB Eindhoven Netherlands Univ Estado Rio De Janeiro Rio De Janeiro Brazil

Reconfigurable systems, exploiting a mixture of the traditional CPU-centric instruction-stream-based processing with the decentralized parallel application-specific data-dominated processing, provide a drastically higher performance and lower power consumption than the traditional CPU-centric systems. They do it at much lower costs and shorter times to market than the not reconfigurable hardware solutions. They also provide the flexibility that is often required for engineering of modern robust and adaptive systems. Due to their heterogeneity, flexibility and potential for highly optimized application-specific instantiation, the reconfigurable computing (RC) systems are adequate for a very broad class of applications across different industry sectors. In this paper, the basic definitions, concepts and features of reconfigurable systems are discussed, as well as their role, purposes they serve and applications that can significantly benefit from them. Also, a comparison of the hardwired systems, RC systems and CPU-centric systems is made, and some main concepts of an effective and efficient reconfigurable computing are discussed. Subsequently, the classification of the RC systems is introduced and their various architecture classes are overviewed. This is followed by a discussion of some major drivers and requirements of the recent and future developments in the modern RC system area, and an overview of the recent and future development trends in the RC architectures. The reconfigurable system area is a very promising, but quite a new field. New opportunities have been opened for this field through introduction of the system-on-a-chip technology, and a big progress has been made in the recent years. Many different reconfigurable devices and computers became commercially available. Nevertheless, multiple aspects of the RC systems, their development and their supporting tools still belong to the open research or development topics.

关键词： Embedded systems reconfigurable systems reconfigurable computing computer architectures coarse-grained architectures heterogeneous architectures

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