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39th Midwest Symposium on Circuits and Systems

作者： Mourad, S Santa Clara Univ Santa Clara United States

ISBN: (纸本)0780336372

This paper describes a novel approach to teaching an advanced logic design course at the undergraduate level. The emphasis is on the use of different CAD tools as 1) a vehicle to accelerate the student learning, 2) a means to demonstrate design approaches and implementations, 3) an instrument to measure circuit parameters, and 4) an opportunity to prepare the students for their careers. Course assessment through examination results and course evaluation indicates that the CAD tools have helped clarify and reinforce the concepts learned in the lectures and have aided the students' ability to incorporate the algorithmic nature CAD tools in their design process.

关键词： computer aided logic design

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Hierarchical Reaction logic Enables Computational design of Complex Peptide Syntheses

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JOURNAL OF THE AMERICAN CHEMICAL SOCIETY 2025年第9期147卷 7644-7662页

作者： Molga, Karol Beker, Wiktor Roszak, Rafal Czerwinski, Andrzej Grzybowski, Bartosz A. Allchemy Inc Highland IN 46322 USA Polish Acad Sci Inst Organ Chem PL-01224 Warsaw Poland IBS Ctr Algorithm & Robotized Synth CARS Ulsan 689798 South Korea UNIST Dept Chem Ulsan 689798 South Korea

The prevalent assumption in computer-assisted synthesis planning has been to rely on the wealth of reaction data and on the consideration of this vast knowledge base at every stage of route planning. Yet even if equipped with all requisite knowledge of individual reaction transforms and state-of-the-art search algorithms, the existing programs struggle when confronted with advanced targets, such as the complex peptides this work considers. By contrast, when the searches are constrained by hierarchical logic, dictating which subsets of reactions to apply at different stages of synthesis planning, these algorithms are able to plan, within minutes, complete routes to clinically relevant targets as complex as vancomycin and as large as semaglutide. Despite not being trained on any literature precedents, the routes designed by the algorithm mimic the strategies used by human experts. The hierarchical planning we describe incorporates protecting-group strategies and realistic pathway pricing and can be performed in solid-state or solution modes, in the latter case using either C-to-N or N-to-C peptide extension strategies.

关键词： computer aided logic design

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Weight-Based Bose–Lin Codes in Concurrent Error-Detection Circuit Based on Boolean Signal Correction

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Journal of computer and Systems Sciences International 2025年第1期64卷 17-35页

作者： Yelina, Y.I. Efanov, D.V. Peter the Great St. Petersburg Polytechnic University St. Petersburg195251 Russia Russian University of Transport Moscow127994 Russia

This paper explores the possibilities of using weight-based Bose–Lin codes in the synthesis of a concurrent error-detection circuit based on Boolean signal correction. The dependencies of the number of weighting options in the construction of the considered class of codes on the number m of data symbols are established. It is shown that with an increase in the value of the number m, the number of weighting methods increases significantly, which makes it possible to build a large number of codes and, as a result, have greater variability in the construction of a self-checking device. The patterns that appear when the number of data symbols changes are established, linking the number of weighting options when building the code. It is shown that the number of ways to synthesize concurrent error-detection circuits based on Boolean signal correction using weight-based Bose–Lin codes factorially depends on the number of allocated data symbols among the data signals of the diagnostic object. The examples given in the paper demonstrate the effectiveness of using weight-based Bose–Lin codes in the synthesis of a concurrent error-detection circuit compared to using the traditional method based on duplication. It is advisable to take the results of the study into account when developing self-checking digital devices, as well as when developing their computer-aided design systems. © Pleiades Publishing, Ltd. 2025.

关键词： computer aided logic design

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Compact Analytical Model for a Raised Buried Oxide Ferroelectric TFET for RF/Analog Applications and Its Implementation as an Inverter

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Journal of Electronic Materials 2025年 1-18页

作者： Meriga, Sirisha Chowdary, M. Kalpana Bhowmick, Brinda Ganesh, C. Kota, Venkata Ramarao Chalapathi Institute of Engineering and Technology Guntur India BVRIT Hyderabad College of Engineering for Women Hyderabad India National Institute of Technology Silchar Silchar India Sri Eshwar College of Engineering Coimbatore Coimbatore India

In this paper, an inventive analytical modeling of drain current for the silicon-on-insulator (SOI)-raised buried oxide (RBOX) ferroelectric gate (Fe) tunnel field-effect transistor (TFET) laid on the tunneling window is proposed. Utilizing this model, the critical parameters for direct-current (DC) and radio-frequency (RF)/analog applications, such as the output current (Id), the transconductance (gm), its efficiency factor (gm/Id), and the cutoff frequency (Ft) have been computed based on the tunneling window voltage, electric field, Urbach energy, and the current onset. The Urbach energy factor and the electric field based on the thickness and the voltage drop across it, the ferroelectric layer (tFe and VFe), the remanent polarization (Pr), the coercive field (Ec), the anisotropic constants (⍺Fe and βFe), the material's inherent constants, and a few fitting parameters proved the proposed model’s validation for the DC and RF/analog applicability in ultralow-power and high-speed applications. The authentication of this model has been confirmed using the simulation results of the proposed device using the two-dimensional (2D) Synopsys TCAD (technology computer-aided design) environment. The proposed device off- and on-state currents are 7.39 × 10−13 A/μm and 3.53 × 10−4 A/μm, respectively, with a subthreshold slope of 30.76 mV/dec and transconductance of 7.35 × 10−3 S/μm along with a cutoff frequency of 71 THz. This analytical model can be readily adapted to estimate and interpret the RF/analog performance parameters of any negative-capacitance ferroelectric gate TFET, and the comparison of the various performance parameters with the existing TFETs proves its outstanding efficacy. The operation of the SOI-RBOX-Fe TFET as an inverter is also investigated for digital applicability. © The Minerals, Metals & Materials Society 2025.

关键词： computer aided logic design

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Large Language Models for EDA: From Assistants to Agents

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FOUNDATIONS AND TRENDS IN ELECTRONIC design AUTOMATION 2025年第4期14卷 295-314页

作者： He, Zhuolun Pu, Yuan Wu, Haoyuan Qin, Yuhan Qiu, Tairu Yu, Bei Chinese Univ Hong Kong Hong Kong Peoples R China ChatEDA Tech Hong Kong Peoples R China

This survey explores the application of Large Language Models (LLMs) in Electronic design Automation (EDA), covering their roles as both assistants and autonomous agents. We review current research and practical implementations where LLMs are utilized for tasks such as question answering, script generation, and automated design processes. This work highlights the benefits of LLMs, including enhanced productivity and innovation, while also addressing challenges like accuracy and integration with traditional EDA tools. Furthermore, we discuss the evolution from LLMs as supportive assistants to more sophisticated agents capable of handling complex EDA workflows. This work aims to provide a comprehensive overview and guide future advancements in the integration of LLMs within the EDA domain.

关键词： computer aided logic design

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A Hierarchical Multilevel Modeling Framework for the Creation of High-Quality Solid Models in Parametric Feature-Based CAD Systems

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computer-aided design and Applications 2025年第2期22卷 229-244页

作者： Company, Pedro Contero, Manuel Camba, Jorge D. Aranburu, Aritz Justel, Daniel Universitat Jaume I Spain Universitat Politècnica de València Spain Purdue University United States Mondragon Unibertsitatea Spain

Building on the premise that quality is a complex and multifaceted concept, we advocate for the structuring of the concept of quality in engineering design parametric CAD modeling by using three hierarchical levels. The goal is to successfully parse whether CAD models are usable, reusable, and semantically rich. Our classification results from emphasizing three sequential objectives that the models must accomplish: (1) being free from geometric and topological errors, (2) being modifiable without causing regeneration errors that may hinder reusability, and (3) being able to properly convey design intent while enabling design exploration and enabling CAD models to become digital twins. In this paper, we elaborate on the proposed framework and discuss its implications. Our grouping facilitates the matching of the six dimensions, which cover all aspects of CAD quality, with the two more commonly considered aspects of usability and reusability. Additionally, it highlights the fact that the third level is generally ignored and that the three aspects must be arranged and considered in a sequential manner. Finally, it opens the door to further advances in the automatic quantification of parametric CAD quality. © 2025 U-turn Press LLC.

关键词： computer aided logic design

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2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop 24

2024 ICCAD CAD Contest Problem B: Power and Timing Optimizat...

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43rd International Conference on computer-aided design, ICCAD 2024

作者： Yang, Sheng-Wei Hsu, Jhih-Wei Li, Ting Wei Chen, Tzu-Hsuan Shen, Chin-Fang Cindy Synopsys Inc. No. 25 Industry East Road IV Science-Based Industrial Park Hsinchu Taiwan

ISBN: (纸本)9798400710773

In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in modern semiconductor designs through the strategic use of multibit flip-flops. By banking flip-flops, more area can be freed up, and also efficiently reduce power consumption and reduce net routing complexity. While multibit flip-flop banking has been effective in reducing power and area, it could negatively impact timing performance in critical paths, thus multibit flip-flop debanking could be performed to alleviate timing critical paths. 2024 ICCAD CAD Contest Problem B presents a challenge where participants must optimize the virtual designs by dynamically applying banking and debanking techniques to achieve optimized trade-offs among PPA. © 2024 Copyright is held by the owner/author(s).

关键词： computer aided logic design

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Practical PCB design Considerations for GaN HEMTs Based Isolated DC-DC Converter 14

Practical PCB Design Considerations for GaN HEMTs Based Isol...

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14th Annual IEEE Applied Power Electronics Conference and Exposition, APEC 2025

作者： Gauttam, Gaureej Krishnamoorthy, S. Pasupuleti, Sai Sushma University of Houston Houston United States

ISBN: (纸本)9798331516116

This paper proposes improved PCB design techniques for converters using Gallium Nitride High Electron Mobility Transistors (GaN HEMTs). An isolated DC-DC converter designed for high-temperature (>150 °C) applications-such as defense, oil and gas, etc.- is considered as the test case for validating the proposed concepts. The primary focus of this paper is to address the challenge of reducing voltage spikes in the drain-to-source voltage (Vds) by minimizing parasitic elements, thereby improving voltage quality in high power density GaN HEMT designs. The proposed 'closed-form' layout for a half-bridge configuration effectively decreases the parasitic inductances, a significant stride in enhancing voltage stability and overall device *** (Q3D analysis) simulations, for the conventional designs and the proposed closed-form layout are done and results are compared. These simulation results are validated through hardware experiments, providing comprehensive confirmation of the design's effectiveness. It is shown that the proposed closed-form layout of GaN HEMT presents a substantial reduction in the Vds spikes. © 2025 IEEE.

关键词： computer aided logic design

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On the Implementation of Capacitance Models in Electronic computer-aided design Tools

On the Implementation of Capacitance Models in Electronic Co...

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2025 International Workshop on Integrated Nonlinear Microwave and Millimetre-Wave Circuits, INMMiC 2025

作者： Angelov, Iltcho Fager, Christian Rorsman, Niklas Chalmers University of Technology Microwave Electronics Laboratory Department of Microtechnology and Nanoscience Göteborg Sweden

Different types of CAD capacitance implementation procedures are discussed: Capacitance, Charge, Total charge, and Charge-Current. The last two models are now implemented and available in commercial CAD tools ADS and ... 详细信息

ISBN: (纸本)9798331519605

关键词： computer aided logic design

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Performance improvement of gate-all-around (GAA) devices by optimized super-steep retrograde well

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Microelectronics Journal 2025年 161卷

作者： Li, Qingkun Zhang, Qingzhu Cao, Lei Li, Lianlian Zhang, Xuexiang Niu, Chuqiao Sang, Guanqiao Bao, Yunjiao Yin, Huaxiang Wu, Zhenhua State Key Laboratory of Fabrication Technologies for Integrated Circuits Institute of Microelectronics of the Chinese Academy of Sciences China School of Integrated Circuits University of Chinese Academy of Sciences China School of Physics Zhejiang University Hangzhou310000 China

This paper systematically investigates the super steep retrograde well (SSRW) scheme to improve performance and optimize short-channel effects (SCEs) in vertically stacked multi-nanosheet field-effect transistors (NSFETs). The trade-off between the performance and leakage of super-steep retrograde well NSFETs is systematically investigated through calibrated three-dimensional technology computer-aided design simulations. The advantages of the proposed technique are demonstrated in actual devices, showing a 66 % and 88.2 % reduction in off-state leakage, as well as an 806.78 % and 320.59 % increase in the on-off current ratio of N/P NSFETs. Additionally, there is an improved sub-threshold slope and drain-induced barrier lowering effect. The proposed scheme achieves these performance gains with minimal additional processing complexity, offering a practical strategy for advancing the power efficiency and scalability of GAA architectures. © 2025 Elsevier Ltd

关键词： computer aided logic design

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