This paper describes a novel approach to teaching an advanced logicdesign course at the undergraduate level. The emphasis is on the use of different CAD tools as 1) a vehicle to accelerate the student learning, 2) a ...
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ISBN:
(纸本)0780336372
This paper describes a novel approach to teaching an advanced logicdesign course at the undergraduate level. The emphasis is on the use of different CAD tools as 1) a vehicle to accelerate the student learning, 2) a means to demonstrate design approaches and implementations, 3) an instrument to measure circuit parameters, and 4) an opportunity to prepare the students for their careers. Course assessment through examination results and course evaluation indicates that the CAD tools have helped clarify and reinforce the concepts learned in the lectures and have aided the students' ability to incorporate the algorithmic nature CAD tools in their design process.
The prevalent assumption in computer-assisted synthesis planning has been to rely on the wealth of reaction data and on the consideration of this vast knowledge base at every stage of route planning. Yet even if equip...
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The prevalent assumption in computer-assisted synthesis planning has been to rely on the wealth of reaction data and on the consideration of this vast knowledge base at every stage of route planning. Yet even if equipped with all requisite knowledge of individual reaction transforms and state-of-the-art search algorithms, the existing programs struggle when confronted with advanced targets, such as the complex peptides this work considers. By contrast, when the searches are constrained by hierarchical logic, dictating which subsets of reactions to apply at different stages of synthesis planning, these algorithms are able to plan, within minutes, complete routes to clinically relevant targets as complex as vancomycin and as large as semaglutide. Despite not being trained on any literature precedents, the routes designed by the algorithm mimic the strategies used by human experts. The hierarchical planning we describe incorporates protecting-group strategies and realistic pathway pricing and can be performed in solid-state or solution modes, in the latter case using either C-to-N or N-to-C peptide extension strategies.
In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in mo...
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Building on the premise that quality is a complex and multifaceted concept, we advocate for the structuring of the concept of quality in engineering design parametric CAD modeling by using three hierarchical levels. T...
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This paper systematically investigates the super steep retrograde well (SSRW) scheme to improve performance and optimize short-channel effects (SCEs) in vertically stacked multi-nanosheet field-effect transistors (NSF...
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TIMEDIAG/GENRAND is a tool set used on various portions of the CMOS processor for the IBM S/390(R) Parallel Enterprise Server Generation 4 to assist in designer-level logic verification, The concept of surrounding the...
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TIMEDIAG/GENRAND is a tool set used on various portions of the CMOS processor for the IBM S/390(R) Parallel Enterprise Server Generation 4 to assist in designer-level logic verification, The concept of surrounding the logicdesign (hereafter referred to simply as ''logic'') under test with irritator behaviorals, a methodology developed and proven effective on larger simulation models, is moved to the designer level without the overhead of writing multiple behaviorals. Rather than writing source-level (e.g., VHDL, C code, etc.) behaviorals, the method creates an external stimulus to the design by using a series of generalized timing diagrams that obey the interface protocols of the logic under test, These timing diagrams are entered using the TIMEDIAG (timing diagram) editor, The effort required for logic verification is thus limited to understanding and laying out the interfaces to the design-a task that must be done for any well-designed unit of logic, regardless of whether or not it is being verified at the designer level, Once the timing diagrams are written, GENRAND (general random driver) is invoked to run simulation on the design, GENRAND randomly initiates the timing diagrams that obey the interface protocol, causing many different input and output permutations, This simulation is very effective in testing the logic implementation.
A generalized Boolean decomposition algorithm is formulated to map a Boolean function into a network of universal cells capable of implementing any function with a fixed number of inputs and outputs. The method is app...
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A generalized Boolean decomposition algorithm is formulated to map a Boolean function into a network of universal cells capable of implementing any function with a fixed number of inputs and outputs. The method is applied to several standard benchmarks and the results presented. When the algorithm is targeted at a technology-specific multi-input cell structure, the cell count is reduced considerably.
Using Maxwell's equations subject to suitable boundary conditions, a preliminary investigation of the propagation characteristics of a tapered optical fiber with helical windings is performed. Eigenvalue relations...
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Using Maxwell's equations subject to suitable boundary conditions, a preliminary investigation of the propagation characteristics of a tapered optical fiber with helical windings is performed. Eigenvalue relations are developed followed by the discussion on the cutoff situations. Plots of the dispersion relations are presented corresponding to two particular values of the helical pitch angle, namely 0 degrees and 90 degrees, and the results are compared. It is observed from the dispersion relations that the helix pitch angle would greatly affect the modal characteristics of the guide, making thereby the angle of pitch as one of the dominant controlling parameters, so far as the fiber design is considered. This is further verified through the comparison of results with those obtained for dielectric tapered fibers without helical windings.
FPGA density and performance are rapidly increasing. As a result, designing with an FPGA closely resembles working with complexgate-array or cell-absed chips. You need to choose the synthesis and other high-level desi...
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FPGA density and performance are rapidly increasing. As a result, designing with an FPGA closely resembles working with complexgate-array or cell-absed chips. You need to choose the synthesis and other high-level design tools carefully foryour targeted FPGA family because the proper tools can speed design time and help produce higher performance chips.
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