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EDN 1995年第10期40卷 153-&页

作者： LIU, J PACIFIC, XA Xilinx Asia Pacific

design decisions are far more complex than simply weighing the unit price and NRE charge to determine whether to use FPGAs or ASICs. An analysis of all the variables affecting IC development shows that FPGAs are extre... 详细信息

关键词： computer aided logic design

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Automated temporal partitioning and loop fission approach for FPGA based reconfigurable synthesis of DSP applications

Proceedings - Design Automation Conference

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Proceedings - design Automation Conference 1999年 616-622页

作者： Kaul, Meenakshi Vemuri, Ranga Govindarajan, Sriram Ouaiss, Iyad Univ of Cincinnati Cincinnati OH United States

We present an automated temporal partitioning and loop transformation approach for developing dynamically reconfigurable designs starting from behavior level specifications. An Integer Linear Programming (ILP) model is formulated to achieve near-optimal latency designs. We, also present a loop restructuring method to achieve maximum throughput for a class of DSP applications. This restructuring transformation is performed on the temporally partitioned behavior and results in near-optimization of throughput. We discuss efficient memory mapping and address generation techniques for the synthesis of reconfigurable designs. A Case study on the Joint Photographic Experts Group (JPEG) image compression algorithm demonstrates the effectiveness of our approach.

关键词： computer aided logic design

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Debugging hardware designs using a value-based model

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Applied Intelligence 2002年第1期16卷 71-92页

作者： Wotawa, Franz Technische Universität Graz Institut for Software Technology Inffeldgasse 166/2 A-8010 Graz Austria

In this paper we describe the use of model-based diagnosis for locating bugs in hardware designs. Nowadays hardware designs are written in a programming language. We restrict our view to hardware designs written in a subset of the commonly used hardware description language VHDL. This subset includes all synthesizeable (register transfer level (RTL)) programs, i.e., programs that can be automatically converted into a gate level representation. Therefore almost all VHDL programs are RTL programs. We show the conversion of VHDL programs into a logical representation. This representation is a model that can be directly used by a model-based diagnosis engine for computing diagnoses. The resulting diagnoses are mapped back to the VHDL code fragments of the original program explaining a misbehavior. In addition, we specify some rules optimizing the obtained results. We further present some arguments showing that the proposed debugging technique scales up to large designs.

关键词： computer aided logic design

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Comparative Analysis of the Controllers for PUMA 560 Robot

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IFAC-PapersOnLine 2016年第25期49卷 98-103页

作者： Joki, Dejan . Lubura, Slobodan D. Faculty of Electrical Engineering East Sarajevo East Sarajevo71123 Bosnia and Herzegovina

Regarding the fact that the industrial robot PUMA 560 is one of the robots with the best mathematical description of its kinematics, it found the new application in the research laboratories for educational purposes. For that reason there is a need to design new controllers which would be compatible with the contemporary CAD tools used for robot movement programming in a graphic manner. Basically, new controllers can be divided into two groups: PC-based and with embedded computer. It is well established that PC computers are known for their unreliability and sensitivity to computer viruses and the suggestion is that the stated shortcomings should be overcome by the use of FPGA based embedded computers. In this paper is suggested FPGA based controller which has to answer the following requirement of the hypothesis: realisation of the robot controller based on FPGA chip (single chip) which contributes the system availability and safety while answering all the functional, safety and economical requirements. The new controller will enable the use of advance CAD tools which is one of the aims of the research. © 2016

关键词： Controllers Algorithms computer aided design computer aided logic design computer control computer viruses Digital circuits Field programmable gate arrays (FPGA) Industrial research Machine design Research laboratories Robot programming Robots Arm movements Comparative analysis Embedded computers FPGA based controller Mathematical descriptions Robot controller Robot controls System availability

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Accurate area and delay estimation from RTL descriptions

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 1998年第1期6卷 168-172页

作者： Srinivasan, A Huber, GD LaPotin, DP Mentor Graph Corp San Jose CA 95131 USA IBM Personal Syst Prod Austin TX USA IBM Austin Res Lab Austin TX USA

In this paper, we present a method for efficiently obtaining area and delay estimates from RTL descriptions of a logic design, The estimates are obtained through fast compiler-type optimizations on the RTL descriptions followed by application of best-fit polynomial area and delay models on the resulting technology-independent representation. The estimation techniques were incorporated into a tool called QUEST. QUEST was used by designers of a large commercial CPU to obtain quick feedback on the area and delay impact of behavioral modifications, resulting in significant savings in design schedule.

关键词： circuit CAD circuit optimisation delays logic CAD polynomials QUEST tool RTL descriptions area estimation best-fit polynomial models delay estimation estimation techniques fast compiler-type optimizations logic design technology-independent representatio area estimation Estimation Techniques delay estimation Polynomial computer aided logic design logic design Circuit optimization delay design schedule circuit CAD

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logic based design modeling with shape algebras

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Automation in construction 1997年第4期6卷 311-322页

作者： Chase, S.C. Natl Inst of Standards and Technology Gaithersburg United States

A new method of describing designs by combining the paradigms of shape algebras and predicate logic representations is presented. Representing shapes and spatial relations in logic provides a natural, intuitive method of developing complete computer systems for reasoning about designs. The advantages of shape algebra formalisms over more traditional representations of geometric objects are discussed. The method employed involves the definition of a large set of high level design relations from a small set of simple structures and spatial relations. Examples in architecture and geographic information systems are illustrated.

关键词： computer aided logic design

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Formal verification and diagnosis of combinational circuit designs with propositional logic

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Fundamenta Informaticae 1997年第1期31卷 79-105页

作者： Lee, Shie-Jue Lin, Wei-Jer Natl Sun Yat-Sen Univ Kaohsiung Taiwan

Zero-defect is extremely important for VLSI designs. Formal techniques for verifying the correctness of logic designs overcome the limits of test case simulation. Many formal systems have been proposed for verification purpose. However, verification of VLSI designs is not enough. It would be equally or more important to correct wrong designs. Little attention has been paid on diagnosis of logic designs. We propose a formal system, based on a propositional logic theorem prover, to verify a combinational logic design and to fix the design if it is incorrect. By referring to the models obtained for an incorrect design and applying some heuristics, the system can locate errors and correct the design in an intelligent way.

关键词： computer aided logic design

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Construction of a bearing testing apparatus to assess lifetime of large-scale bearings

Communications - Scientific Letters of the University of Ži...

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Communications - Scientific Letters of the University of Žilina 2009年第2期11卷 57-64页

作者： Hrcek, Slavomir Kraus, Vaclav Kohar, Robert Medvecky, Stefan Lehocky, Pavol Faculty of Mechanical Engineering University of Zilina Slovakia Faculty of Electrical Engineering University of Zilina Slovakia

This article discusses steps towards the design, construction and production of a device used for lifetime assessment of large-scale bearings. The machine is reviewed as a mechatronic entity, comprised of three parts - mechanical, electro technical and hydraulic. The mechanical part was designed with the help of modern CAD/CAE/PDM design systems along with device parts modeling and strength analysis of highly stressed device parts. The electrotechnical part consists of a driving unit - containing the frequency transducer and an asynchronous motor;the PLC-driven operating part together with a touchscreen interface and a monitoring part which includes a datalogging device to record measurement results and interface with a PC.

关键词： computer aided logic design

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FPGA circuit optimization using block integration based on multiple output capability

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Systems and computers in Japan 1999年第11期30卷 12-21页

作者： Kouda, Takenori Kambayashi, Yahiko Department of Information Science Kyoto University Kyoto 606-8501 Japan Department of Social Informatics Kyoto University Kyoto 606-8501 Japan

A logic optimization technique for Field Programmable Gate Arrays (FPGAs) is proposed. To achieve further block integration, permissible functions and error compensation procedures are used. The effectiveness of the proposed method is shown by MCNC benchmarks. Experimental results show that the number of blocks related to chip area closely is 37% reduced on average.

关键词： computer aided logic design

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CHARACTERIZATION AND design OF GAAS SCFL LATCHED COMPARATORS BASED ON IMPROVED LINEARIZED MODELS

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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-FUNDAMENTAL THEORY AND APPLICATIONS 1995年第6期42卷 362-366页

作者： FENG, S SELTZER, D FRAUNHOFER INST INTEGRATED CIRCUITS D-91058 ERLANGENGERMANY

This brief presents characterization and design considerations of high-speed and high-precision GaAs latched comparators consisting of source coupled FET logic (SCFL) flip flops. In order to characterize the comparators, linearized equivalent circuit models are improved for the SCFL hip flops. Based on the models, critical design parameters such as recover time, regeneration time and input voltage sensitivity are determined for the comparators. Circuit configurations for increasing circuit speed and accuracy are characterized and compared. One comparator is optimized and implemented in a 0.5 mu m GaAs E/D HEMT technology. Measurement results demonstrate the implemented comparator achieves an average voltage sensitivity of 115 mV at low frequencies and an optimal voltage sensitivity of 10.0 mV at an input signal frequency of 2 GHz and a clock frequency of 4 GHz. Predicted voltage sensitivities are also verified to be in good agreement with the measured results.

关键词： HEMT integrated circuits III-V semiconductors comparators (circuits) equivalent circuits field effect logic circuits flip-flops gallium arsenide logic CAD sequential circuits 0.5 micron 10.0 mV 11.5 mV 2 GHz 4 GHz E/D HEMT technology GaAs SCFL latched co gallium arsenides voltage sensitivity equivalent circuits sequential circuits flip-flops computer aided logic design III-V semiconductors COMPARATORS HEMT integrated circuits clock frequency

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