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Conceptual framework for the design of logic control

Intelligent systems engineering 1993年第4期2卷 246-256页

作者： Ferrarini, L. Maffezzoni, C. Dipartimento di Elettronica e Informazione Politecnico di Milano Milano Italy

A conceptual and practical environment to design logic controllers is presented, which is based on a special version of Petri nets tailored to this aim. One of the purposes is to not only provide control engineers with powerful graphic tools to manipulate designs quickly and simulation tools to check system performance in particular operative conditions, but also with analytic tools to formally verify controller correctness. Most of the theoretical analysis links to algebraic theory of Petri nets with the fundamental concepts of net invariants and dead-locks. An example from an electrical power plant field is thoroughly examined through all design stages.

关键词： computer aided logic design

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A systematic review of assessment and intervention strategies for effective clinical communication in culturally and linguistically diverse students

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MEDICAL EDUCATION 2016年第9期50卷 898-911页

作者： Chan, Annie Purcell, Alison Power, Emma Univ Sydney Fac Hlth Sci Speech Pathol Cumberland Campus C42POB 170 Lidcombe NSW 1825 Australia

OBJECTIVE Culturally and linguistically diverse (CALD) students often experience difficulties with the clinical communication skills that are essential for successful interactions in the workplace. However, there is little evidence on the effectiveness of assessment and intervention strategies for this population. The two aims of this study were: to evaluate the effectiveness of assessment tools in identifying and describing the clinical communication difficulties of CALD health care students;and to determine whether communication programmes improved their clinical communication skills. METHODS Systematic review based on the Cochrane protocol. Articles were identified through a search of established databases using MeSH and key search terms. Studies published in English from 1990 to March 2015 were included if they described assessment strategies or a training programme for communication skills of CALD students. Studies were excluded if they did not describe implementation of a specific assessment or intervention programme. Data were extracted independently by the first author and verified by the second author. Quality was measured by the Best Evidence Medical Education guide and the Educational Interventions Critical Appraisal Tool. The Kirkpatrick hierarchy was used to measure impact. Meta-analysis was not conducted because of the heterogeneity of programme design and outcome measures. RESULTS One hundred and twenty-nine articles met the criteria for full text review. Eighty-six articles were excluded. Thirteen articles addressing assessment and 30 articles reporting on communication training programmes were included in this review. Assessment tools used rubrics and rating scales effectively. Intervention studies focused on speech and language skills (n = 20), interpersonal skills (n = 7) and faculty-level support (n = 5). Although 17 studies reported positive findings on student satisfaction, only eight reported improved skills post-training. CONCLUSIONS The deve

关键词： Intervention Medical Communication Skills Communication Research computer aided logic design Review, Systematic Students

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design of a fast and area efficient multi-input muller C-element

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IEEE Transactions on Very Large Scale Integration (VLSI) Systems 1993年第2期1卷 215-219页

作者： Wuu, Tzyh-Yung Sarma, B.K.Vrudhula Univ of Southern California Los Angeles United States

A multi-input Muller C-element has frequently been used for joining signal transitions or completion time detection self-timed circuits. This paper presents an n-input Muller C-element design which uses the multi-level login design technique and has a symmetric format for any integer n≥ 2. In comparison with series-parallel MOS structure implementations and C-element tree implementations, our design has fewer restrictions in terms of n, less path delay, less delay variance from inputs to output, and less area consumption. Experimental validation in this paper is based on an industrial standard cell library.

关键词： computer aided logic design

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Matching analogue models with reality

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IEE Electronics Systems and Software 2003年第5期1卷 32-35页

作者： Hayes, Julian Marketing Wolfson Microelectronics

The issues concerned with the analog and mixed signal circuit designs are discussed. Analog circuits require high expertise level, time and effort in their designing when compared with their digital counterparts. Analog designs use guard bands and error-compensating designs rather than models that ensure good design. The utilization of 1/f noise model in the designing process and the aspects of using analog designs in package modeling are also highlighted.

关键词： computer aided logic design

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Area-IO DRAM/logic integration with System-in-a-Package(SiP) 05

Area-IO DRAM/logic integration with System-in-a-Package(SiP)

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10th Asia and South Pacific design Automation Conference

作者： Wang, Anru Dai, Wayne Univ Calif Santa Cruz Dept Comp Engn Santa Cruz CA 95064 USA

ISBN: (纸本)0780387368

This paper presents a cost-effective area-IO DRAM (aDRAM)/logic integration implemented with CLC (Chip-Laminate-Chip)-based System-in-a-Package (SiP) technology. By inserting 512 area-IOs into the area-IO DRAM, the bandwidth of the area-IO DRAM can achieve 10GB/s when working under 166MHz. An interface module with configurable 10 width was also developed to make this implementation platform able to be adapted by various applications. A performance analysis, including bandwidth and power is also presented in this paper. It is demonstrated that area-IO DRAM/logic integration with SiP technology provides significant cost-effective implementation methodology compared with embedded DRAM and off-chip DRAM.

关键词： DRAM chips chip scale packaging VHF circuits integrated circuit design circuit CAD logic CAD logic integration cost-effective area-IO DRAM aDRAM CLC-based system-in-a-package technology chip-laminate-chip interface module configurable IO width SiP technology 10 GByte/s 166 MHz interface module VHF circuits computer aided logic design DRAM chips circuit CAD integrated circuit design system-in-package

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SimP: A core for FPLD-based custom-configurable processors

SimP: A core for FPLD-based custom-configurable processors

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2nd International Conference on ASIC

作者： Salcic, Z Maunder, B Univ of Auckland Auckland New Zealand

ISBN: (纸本)7543909405

Standard building blocks play a very important role in the use of new semiconductor technologies such as field programmable logic devices (FPLDs). New design methodologies, that will increase designer productivity and the general quality of design, are necessary in order to use the power of FPLDs especially in embedded applications. One of the promising methods is the merging of the hardware and software parts of the solution, where general processor cells become very important as the core of software part of solution, in the custom computing machine. In this paper de present a new general purpose simple processor cell which is easily implemented in an FPLD and used as a library block that can be extended or combined with other library cells to form custom application-specific configurations.

关键词： computer aided logic design

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Distributed logic simulation algorithm using preemption of inconsistent events

Distributed logic simulation algorithm using preemption of i...

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11th International Conference on VLSI design

作者： Raghu, CS Sundaram, S Texas Instruments India Ltd ASIC Div Bangalore 560017 Karnataka India

ISBN: (纸本)0818682248

Parallel Processing offers a viable alternative to improve the enormous execution time of logic simulation of large VLSI designs. Various parallel logic simulation schemes have been proposed in recent years on achieving speedup using conservative and optimistic asynchronous algorithms. In this paper, we have proposed a new algorithm, capable of preempting inconsistent events and also reducing the number of messages sent among processors, resulting in faster simulation. Usage of prediction time, in both sequential and combinational circuits, gives capability of preempting inconsistent events and thereby supporting the rise/fall delay model for conservative event driven simulation. Implementation of the proposed algorithm has been carried out in a network of IBM RISC 6000/300 system workstations. Results of the proposed algorithm is compared with the null message based CM algorithm, and it was found that proposed algorithm works efficiently compared to the CM algorithm in case of sequential circuits and works as good as CM algorithm in combinational circuits.

关键词： computer aided logic design

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Scheduling using behavioral templates 95

Scheduling using behavioral templates

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32nd design Automation Conference

作者： LY, T KNAPP, D MILLER, R MACMILLEN, D SYNOPSYS INC MT VIEWCA 94043

ISBN: (纸本)0897916530

This paper presents the idea of 'behavioral templates' in scheduling. A behavioral template locks several operations into a relative schedule with respect to one another. This simple construct proves powerful in addressing: (1) timing constraints, (2) sequential operation modeling, (3) pre-chaining of certain operations, and (4) hierarchical scheduling. We present design examples from industry to demonstrate the importance of these issues in scheduling.

关键词： computer aided logic design

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Synthesis support for design partitioning

Synthesis support for design partitioning

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1997 IEEE International Verilog HDL Conference

作者： Willoughby, J Cadence Design Systems San Jose United States

ISBN: (纸本)0818679557

As designs become larger and larger it becomes necessary to partition the design, not only to meet synthesis tool restrictions, but also to perform parallel design processing by multiple engineers and/or on multiple machines. Partitioning requires the assignment of timing and loading budgets across module boundaries. This is an inefficient and time-consuming task if performed by hand. logic Synthesis tools can utilize techniques of constraint propagation combined with hierarchical controls to perform this task automatically. This approach will result in improved results and shorter design times.

关键词： computer aided logic design

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Architecture and compilation for data bandwidth improvement in configurable embedded processors

Architecture and compilation for data bandwidth improvement ...

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IEEE/ACM International Conference on computer aided design

作者： Cong, J Han, GL Zhang, GF Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

ISBN: (纸本)078039254X

Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, recent study has shown that the limited data bandwidth available in the core processor (e.g., the number of simultaneous accesses to the register file) becomes a serious performance bottleneck. In this paper we propose a new low-cost architectural extension and associated compilation techniques to address the data bandwidth problem. Specifically, we embed a single control bit in the instruction op-codes to selectively copy the execution results to a set of hash-mapped shadow registers in the write-back stage. This can efficiently reduce the communication overhead due to data transfers between the core processor and the custom logic. We also present a novel simultaneous global shadow register binding with a hash function generation algorithm to take full advantage of the extension. The application of our approach leads to a nearly-optimal performance speedup (within 2% of the ideal speedup).

关键词： embedded systems integrated circuit design logic CAD microprocessor chips architectural extension techniques associated compilation techniques automatic instruction set configurable embedded processors core processor custom logic data bandwidth data tran computer aided logic design Microprocessor chips integrated circuit design Embedded systems PROCESSOR Collected papers register file configurability Bandwidth Building construction ARCHITECTURE instruction sets embedding

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