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computer 2016年第9期49卷 12-12页

作者： Montuschi, Paolo Muller, Jean-Michel Polytech Univ Turin Turin Italy CNRS F-75700 Paris France

This installment of computer's series highlighting the work published in IEEE computer Society journals comes from IEEE Transactions on computers.

关键词： computer Science Computing computer arithmetic Spotlight On Transactions

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High Efficient GDI-CNTFET-Based Approximate Full Adder for Next Generation of computer Architectures

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IEEE EMBEDDED SYSTEMS LETTERS 2023年第1期15卷 33-36页

作者： Sadeghi, Ayoub Ghasemi, Razieh Ghasemian, Hossein Shiri, Nabiollah Islamic Azad Univ Dept Elect Engn Shiraz *** Iran Iran Univ Sci & Technol Sch Elect Engn Tehran *** Iran Shiraz Univ Technol Dept Elect & Elect Engn Shiraz *** Iran

computing (AC) is an emerging technique in arithmetic circuits. In this letter, a new AC-based full adder (FA) circuit is presented with 12 transistors, 0.239 mu m2 of area, and two errors in the outputs. In the proposed FA, the gate diffusion input (GDI) and dynamic-threshold (DT) techniques are applied using the carbon nanotube field-effect transistor (CNTFET) technology. Accuracy metrics, such as normalized mean error distance (NMED) and mean relative error distance (MRED) along with circuitry parameters of power-delay-product (PDP), energy-delay-product (EDP), and power-delay-area-product (PDAP), confirm the efficiency of the proposed FA for complex structures. The proposed FA is embedded in a ripple carry adder (RCA) by various numbers of approximate bits (NABs), and then the accuracy and circuitry parameters are extracted. Compared to the state-of-the-art designs, the high-efficient behavior of the proposed FA is proved when it is used in image processing applications.

关键词： Logic gates Transistors Delays CNTFETs Inverters Adders computer architecture Approximate computing (AC) carbon nanotube field-effect transistor (CNTFET) computer arithmetic full adder (FA)

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Sparse Matrix-Vector Multiplication Based on Online arithmetic

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IEEE ACCESS 2024年 12卷 87653-87664页

作者： Cherati, Sahar Moradi Jaberipur, Ghassem Sousa, Leonel Univ Lisbon INESC ID P-1049001 Lisbon Portugal Univ Lisbon Inst Superio Tecn P-1049001 Lisbon Portugal Chosun Univ Dept Comp Engn Gwangju 61452 South Korea

Online arithmetic, where computations are performed from the most significant digit first, has shown benefits in improving throughput and latency within high-performance computing. This computational mode is particularly beneficial for intensive data processing in sequential operations, enabling streaming computations. One such intensive operation is sparse matrix-vector multiplication (SpMV) which finds extensive application in various engineering fields. SpMVs are often carried out in compressed formats such as coordinate encoding format that inherently follows a sequential approach to execute multiply-and-accumulate (MAC) operations of sparse elements. Therefore, this paper proposes an online MAC unit, through a novel algorithm and architecture. Moreover, a SpMV unit is developed by integrating the proposed online MAC unit. The performance and efficiency of the proposed MAC design are evaluated against state-of-the-art MAC designs, synthesized using the TSMC 45 nm CMOS standard cell library with the Synopsis Design Compiler. Results demonstrate the superiority of the proposed MAC unit in terms of delay, area-delay product, and energy consumption. Besides, the SpMV employing the online MAC is compared with counterpart SpMV designs implemented in both ASIC and FPGA. The proposed SpMV design outperforms conventional designs in various performance metrics, achieving a speed-up of 1.69 x and energy reductions of up to 60.4% compared to other SpMV designs for 8-bit precision. Moreover, various sparse matrix datasets with different properties are used to evaluate the SpMV using the online MAC unit, considering metrics such as power, delay, hardware resources, and energy consumption.

关键词： arithmetic Sparse matrices Delays Hardware Vectors Field programmable gate arrays Energy consumption Application specific integrated circuits computer arithmetic adder multiplier multiply-and-accumulate (MAC) unit most-significant-digit first arithmetic energy consumption ASIC

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Constraint-Aware E-Graph Rewriting for Hardware Performance Optimization

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2025年第4期44卷 1366-1379页

作者： Coward, Samuel Drane, Theo Constantinides, George A. Intel Corp Numer Hardware Grp Folsom CA 95630 USA Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

Data-dependent constraints commonly occur across hardware and software, often in the form of code branches or input constraints. Expert designers exploit these constraints to realize new optimization opportunities. Numerical hardware designers exploit this aggressively, as if a particular module input value can never be seen, then there is no need to dedicate any circuit area to handling that input value. Floating-point hardware designers have gone further, specifically introducing carefully constructed case-splits to exploit underutilized critical paths. To automate constraint-aware optimization, we developed a theoretical framework, based on the e-graph data structure, that localizes constraint reasoning tasks and makes it simple to realize optimizations exploiting the underlying control structures. The theory introduced here provides an approach to encode multiple equivalence relations within a single e-graph. To demonstrate the value of the theoretical developments, we extend an existing register transfer level (RTL) optimization tool, ROVER, allowing it to exploit constraints present in the RTL itself. We combine this new constraint-awareness with a new RTL value range analysis, allowing ROVER to understand what values each intermediate signal can take. We further add to ROVER by developing a model for circuit delay, allowing ROVER to explore the tradeoffs between performance and circuit area. With these latest developments, ROVER is capable of fully automatically discovering known floating-point architectures from the computer arithmetic literature. The designs generated by constraint-aware ROVER are, on average, 30% faster and 1% smaller than those generated by state-of-the-art EDA tools.

关键词： Optimization Design automation Integrated circuits Hardware Data structures Delays Codes Circuit optimization Software Logic gates computer arithmetic datapath design design automation hardware optimization

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ROVER: RTL Optimization via Verified E-Graph Rewriting

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第12期43卷 4687-4700页

作者： Coward, Samuel Drane, Theo Constantinides, George A. Intel Corp Numer Hardware Grp Santa Clara CA 95052 USA Imperial Coll London Dept Elect & Elect Engn London SW7 2AZ England

Manual register transfer level (RTL) design and optimization remains prevalent across the semiconductor industry because commercial logic and high-level synthesis tools are unable to match human designs. Our experience in industrial datapath design demonstrates that manual optimization can typically be decomposed into a sequence of local equivalence preserving transformations. By formulating datapath optimization as a graph rewriting problem we automate design space exploration in a tool we call *** develop a set of mixed precision RTL rewrite rules inspired by designers at Intel and an accompanying automated validation framework. A particular challenge in datapath design is to determine a productive order in which to apply transformations as this can be design dependent. ROVER resolves this problem by building upon the e-graph data structure, which compactly represents a design space of equivalent implementations. By applying rewrites to this data structure, ROVER generates a set of efficient and functionally equivalent design options. From the ROVER generated e-graph we select an efficient implementation. To accurately model the circuit area we develop a theoretical cost metric and then an integer linear programming model to extract the optimal implementation. To build trust in the generated design ROVER also produces a back-end verification certificate that can be checked using industrial *** apply ROVER to both Intel-provided and open-source benchmarks, and see up to a 63% reduction in circuit area. ROVER is also able to generate a customized library of distinct implementations from a given parameterizable RTL design, improving circuit area across the range of possible instantiations.

关键词： Optimization arithmetic Design automation Hardware design languages Hardware Space exploration Measurement computer arithmetic datapath design design automation hardware optimization

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MSDF-Based MAC for Energy-Efficient Neural Networks

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IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS 2025年

作者： Cherati, Sahar Moradi Barzegar, Mohsen Sousa, Leonel INESC ID P-1000029 Lisbon Portugal Inst Super Tecn Dept Elect & Comp Engn P-1049001 Lisbon Portugal Inst Super Tecn Inst Telecomun P-1049001 Lisbon Portugal

This article presents an energy-efficient serial multiply-accumulate (MAC) unit based on the most significant digit first (MSDF) approach, specifically aimed at neural networks operating in resource-constrained and low-energy environments. The proposed MAC unit has been integrated into two neural network architectures: a multilayer perceptron (MLP) and a denoising autoencoder. For the MLP, we employ a pre-trained model for handwritten digit classification using the Modified National Institute of Standard and Technology (MNIST) dataset. Hardware synthesis using 45 nm CMOS technology shows that the MSDF-based MLP achieves a favorable trade-off between hardware metrics, such as reduced circuit area and energy per neuron, and reaches a good classification accuracy of 97.4%. In the case of the autoencoder, the proposed MAC unit is utilized in a pre-trained denoising autoencoder for the same dataset. The autoencoder employs MSDF-based mixed precision across layers to reduce computational resources and loads while preserving high-quality image reconstruction. A comprehensive evaluation of image correctness, signal fidelity, and visual quality metrics was conducted to assess the impact of varying precision levels across different layers. The results indicate that the proposed approach achieves an effective denoising performance with balanced hardware requirements.

关键词： arithmetic Autoencoders Noise reduction Parallel processing Accuracy Hardware Encoding Delays Biological neural networks Measurement computer arithmetic denoising energy efficiency most significant digit first (MSDF) arithmetic multiply-accumulate (MAC) neural networks

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AxOSpike: Spiking Neural Networks-Driven Approximate Operator Design

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS 2024年第11期43卷 3324-3335页

作者： Ullah, Salim Sahoo, Siva Satyendra Kumar, Akash Ruhr Univ Bochum Chair Embedded Syst D-44801 Bochum Germany Interuniv Microelect Ctr B-3001 Leuven Belgium

Approximate computing (AxC) is being widely researched as a viable approach to deploying compute-intensive artificial intelligence (AI) applications on resource-constrained embedded systems. In general, AxC aims to provide disproportionate gains in system-level power-performance-area (PPA) by leveraging the implicit error tolerance of an application. One of the more widely used methods in AxC involves circuit pruning of arithmetic operators used to process AI workloads. However, most related works adopt an application-agnostic approach to operator modeling for the design space exploration (DSE) of Approximate Operators (AxOs). To this end, we propose an application-driven approach to designing AxOs. Specifically, we use spiking neural network (SNN)-based inference to present an application-driven operator model resulting in AxOs with better-PPA-accuracy tradeoffs compared to traditional circuit pruning. Additionally, we present a novel FPGA-specific operator model to improve the quality of AxOs that can be obtained using circuit pruning. With the proposed methods, we report designs with up to 26.5% lower PDPxLUTs with similar application-level accuracy. Further, we report a considerably better set of design points than related works with up to 51% better-Pareto front hypervolume.

关键词： Accuracy Embedded systems Computational modeling Neurons Spiking neural networks Hardware Space exploration Integrated circuit modeling arithmetic Resilience Accelerator architecture AxC arithmetic circuit design computer arithmetic FPGAs operator modeling SNNs

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Evaluation of new CORDIC algorithms implemented on FPGA for the Givens Rotator

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JOURNAL OF COMPUTATIONAL SCIENCE 2025年 87卷

作者： Poczekajlo, Pawel Moroz, Leonid Deelman, Ewa Gepner, Pawel Koszalin Univ Technol Fac Elect & Comp Sci PL-75453 Koszalin Poland Warsaw Univ Technol Fac Mech & Ind Engn PL-02524 Warsaw Poland Univ Southern Calif USC Informat Sci Inst Marina Del Rey CA 90292 USA

This article is an extended version of our conference paper "Modified CORDIC Algorithm for Givens Rotator" (Poczekajlo et al., 2024) published at the International Conference on Computational Science (ICCS-2024). The CORDIC algorithm is an iterative method of computing trigonometric functions and rotating vectors without using complex calculations. This paper presents two modified CORDIC algorithms for implementing a Givens rotator on FPGA, improving upon classic CORDIC methods. The first approach introduces a selective iteration scheme with an optimized scaling factor, while the second, not published in the original ICCS-2024 paper, leverages a scaling-free methodology for improved precision. Implemented on an Altera Cyclone V FPGA, these algorithms demonstrate a 50% accuracy improvement and a 15% reduction in latency compared to standard methods. These findings contribute to enhanced FPGA-based trigonometric computations, particularly benefiting real-time signal processing and numerical linear algebra applications.

关键词： CORDIC FPGA computer arithmetic

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Design and Analysis of Area and Time Efficient Signed Square Architecture Using Nonconventional Method

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JOURNAL OF CIRCUITS SYSTEMS AND computerS 2025年第5期34卷

作者： Behera, Niharika Pradhan, Manoranjan Bhoi, Bandan Kumar Veer Surendra Sai Univ Technol Dept Elect & Telecommun Engn Burla India

Computing the square of any large signed number using conventional methods is challenging. Therefore, parallel and partial product generation while squaring signed numbers is complex and time-consuming. This paper suggests a very large scale integration design for an efficient signed square architecture using a nonconventional method. The square of a large magnitude signed number is reduced to a lower magnitude signed multiplication and an addition operation by the Yavadunam algorithm. The suggested method finds the deficit of the signed number from the adjacent base to perform the signed square operation. The proposed design is coded using Verilog hardware description language. The synthesis and simulation of this architecture are performed using Xilinx integrated synthesis environment 14.7 software. Furthermore, this architecture is implemented on the Virtex-4, spartan-3 and spartan-6 field programmable gate array devices. The design is also coded in cadence virtuoso centos version 5. Then, it is synthesized using 180nm and 90nm technology. The validation of the proposed architecture is examined using the performance parameters, such as path delay and area. The synthesis results show improvements in delay-area complexity compared to state-of-the-art architectures. The superiority of the proposed architecture is claimed based on performance comparisons with the previous square, multipliers and signed multiplier architectures.

关键词： Signed multiplier square architecture computer arithmetic field programmable gate array Yavadunam algorithm

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Efficient approximate multipliers with adjustable accuracy

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INTERNATIONAL JOURNAL OF ELECTRONICS 2024年第2期111卷 318-337页

作者： Pourkhatoon, Mohammadreza Zarandi, Azadeh Alsadat Emrani Mohammadi, Majid Shahid Bahonar Univ Kerman Dept Comp Engn Kerman Iran

The number of smart devices grows rapidly, and the main leakage of many of these devices is their limited batteries, in addition to the need for a fast and low-power computing system. Approximate calculations are an excellent method for such systems to achieve higher speed and less area and power consumption at the cost of lower accuracy. Furthermore, in many applications with inherent tolerance for insignificant inaccuracies such as image processing, approximate computing can be used to achieve acceptable performance with higher speed, lower power or area consumption. In this work, approximate multiplier structures are proposed based on working on the partial product trees with the aim of reducing area consumption and increasing accuracy. Comprehensive experimental analysis is performed to evaluate the performance of the proposed multiplier in terms of area, delay, power consumption, and accuracy. The results show that our suggested design improves at most 29% of power consumption, 11% of delay, and 55% of the area rather than an exact multiplier. Moreover, the performance of our multipliers is investigated based on the peak signal noise ratio (PSNR) for processing two images, which lead to 56.65 and 23.6 dB.

关键词： Approximate computations computer arithmetic approximate multiplier image processing embedded computing

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