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STANDARDIZED APPROACH FOR ASSESSING FIBER DEVICE RESILIENCY

STANDARDIZED APPROACH FOR ASSESSING FIBER DEVICE RESILIENCY

ASME 2024 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems, InterPACK 2024

作者： Galligan, Conor Alves, Dan MIT Lincoln Laboratory United States

ISBN: (纸本)9780791888469

Fiber-attached photonic devices are critical to myriad government systems, e.g. Laser Communication [1], yet most commercially available photonic devices are not tested to the harsh environments required of fielded systems. While there are well-established guidelines for electronic device component testing, such as NASA's EEE-INST-002 [2], there is no such specification for photonics destined for ruggedized nontelecom environments. This paper presents a specification developed to guide the evaluation of fiber-attached photonic devices for use in ruggedized systems. Component-level testing is specified with the intent of evaluating the likelihood of failure prior to integration into a higher-level assembly, well before system-level environmental testing. This specification was developed leveraging MIT Lincoln Laboratory's decades of experience successfully upscreening fiber devices for use in delivered government prototypes, as well as surveys of government and industry photonic and electronic device standards. The document a) identifies the technical risks inherent in various component types, b) provides a framework to assess the relevance of manufacturers' testing, and c) suggests tests that could be performed to burn down the identified risks as a function of key mission parameters such as environment, cost, schedule, and risk tolerance. Copyright © 2024 by ASME.

关键词： computer debugging

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MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodology with Deep Learning 33

MEMFD: A Multi-EDT Multi-Fault Scan Chain Diagnosis Methodol...

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33rd IEEE Asian Test Symposium, ATS 2024

作者： Siddiqui, Saman Aijaz Patel, Uzair Ruhulamin Jana, Utsav Kumar, Binod Indian Institute of Technology Jodhpur India Upper-Changi Singapore

ISBN: (纸本)9798331529161

Manufacturing defects need to be detected and diagnosed with the help of on-chip test infrastructure. Scan chains are the most important part of the test infrastructure in the modern designs. However, these scan chains also turn out to be crucial defect locations requiring a diagnosis procedure that has severe implications on debug time and root-cause discovery. These problems are further exacerbated by the compression mechanism present in the test infrastructure. Diagnosis methods proposed in the literature mainly suggest techniques based on fault type-based dictionary computation, simulation with input diagnostic patterns and the subsequent analysis of error responses against the inputs. However, these methods do not take into account the advanced test compression infrastructure. In this work, we propose a diagnosis methodology that is based on state-of-the-art multi-embedded deterministic test (EDT) architecture. We utilize deep learning-based analysis methodology for the purpose of identification of the faulty EDT section based on the observed output responses. Experimental results indicate that with lesser overhead in debug time and resources, the proposed methodology can diagnose faulty EDT with a success rate of 85-90%. © 2024 IEEE.

关键词： computer debugging

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Algoviz—Real-Time Insight of Algorithms 3rd

Algoviz—Real-Time Insight of Algorithms

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3rd International Conference on Emerging Trends in Expert Applications and Security, ICE-TEAS 2024

作者： Prasad, S. Ashwini Hanumanthappa, M. Supriyaa, K. Rathore, Vijay Singh Department of Computer Science and Applications Bangalore India Department of Computer Science Engineering Jaipur India

ISBN: (纸本)9789819737444

Algorithms are central objects of every nontrivial computer application but their analysis and design are a great challenge. While traditional methods involve mathematical and empirical approaches, there exists a third avenue for studying algorithms, i.e. the algorithm visualizer. Algorithm visualizer is an interactive software tool designed to enhance the understanding and learning of various algorithms through visual representation. This tool provides a dynamic and engaging way to explore complex computational processes, making them more accessible to both novice learners and experienced programmers. The visualization platform offers a diverse range of algorithms, spanning data structures, sorting methods, graph traversal techniques, path finding algorithms, and more. Through real-time interaction, users gain insights into algorithmic operations, fostering a deeper understanding of their logic and behaviour. Users can customize inputs, experiment with different scenarios, and observe, how algorithmic choice impacts outcomes in a visual and interactive manner. The primary goal of algorithm visualizer is to elucidate the inner workings of various known algorithms by presenting them graphically, thereby simplifying their complexities for comprehension. © The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024.

关键词： computer debugging

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Design and Simulation of Multi-Functional Space Electron Beam Welding Equipment

Design and Simulation of Multi-Functional Space Electron Bea...

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7th International Conference on Electronics Technology, ICET 2024

作者： Yan, Wenjun Yu, Yue Xu, Zihan Beijing University of Technology College of Mechanical Engineering and Applied Electronics Technology Beijing China Beijing University of Technology College of Information Technology Beijing China

ISBN: (纸本)9798350363951

Multi-functional space electron beam welding equipment is a device that utilizes electron acceleration energy for various functions such as material welding, heating, and coating, suitable for use in a vacuum environment. Traditional electron beam welding machines have complex high-voltage power circuit structures and large volumes. To facilitate on-orbit maintenance of space stations and other spacecraft, this study has designed a new type of multi-functional space electron beam equipment, enhancing on-orbit maintenance technology reserves. The equipment specifications, principles, key technologies, and other aspects of the multi-functional space electron beam equipment are briefly discussed. A novel 10 kV / 200 mA inverter-type electron beam welding machine high-voltage power supply is developed with a circuit structure and stable voltage output. The power supply voltage regulation circuit adopts a full-bridge converter controlled by Pulse Width Modulation (PWM) technology, converting the approximately 540 V voltage rectified after three-phase rectification into adjustable stable DC voltage ranging from 0 to 500 V. Subsequently, the voltage is inverted into a 60 kHz square wave AC voltage through a full-bridge inverter circuit. The voltage doubler circuit utilizes a transformer in series with multiplier rectification to convert the preceding 60 kHz square wave AC voltage into a 10 kV DC high voltage. The control circuit employs a voltage dual closed-loop control strategy based on Proportional-Integral-Derivative (PID) regulation, enabling the power supply to achieve stable high-voltage output. This study constructed a Simulink simulation platform for the developed high-voltage power supply and conducted tests, demonstrating stable high-voltage output and high control accuracy. The high-voltage output ripple and stability can both be maintained within a stable range of 0.2%, meeting the requirements of the electron beam welding machine. © 2024 IEEE.

关键词： computer debugging

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Visualizing Logical Correlation in Trace Data for System debugging

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computer 2021年第3期54卷 28-36页

作者： Liu, Chen Intel Santa Clara CA 95054 USA

This article describes a mechanism that enables debug engineers to extract and visualize the logical correlation among events and messages in system-level trace data. It enables debug engineers to focus only on trace ... 详细信息

关键词： computer debugging Data Visualisation Program debugging System debugging Logical Correlation Visualization Trace Packets System Level Trace Data Debug Engineers Correlation Data Visualization debugging Data Mining

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EDA-AWARE RTL GENERATION WITH LARGE LANGUAGE MODELS

arXiv

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arXiv 2024年

作者： ul Islam, Mubashir Sami, Humza Gaillardon, Pierre-Emmanuel Tenace, Valerio PrimisAI Los GatosCA United States University of Utah Salt Lake CityUT United States

Large Language Models (LLMs) have become increasingly popular for generating RTL code. However, producing error-free RTL code in a zero-shot setting remains highly challenging for even state-of-the-art LLMs, often leading to issues that require manual, iterative refinement. This additional debugging process can dramatically increase the verification workload, underscoring the need for robust, automated correction mechanisms to ensure code correctness from the start. In this work, we introduce AIVRIL2, a self-verifying, LLM-agnostic agentic framework aimed at enhancing RTL code generation through iterative corrections of both syntax and functional errors. Our approach leverages a collaborative multi-agent system that incorporates feedback from error logs generated by EDA tools to automatically identify and resolve design flaws. Experimental results, conducted on the VerilogEval-Human benchmark suite, demonstrate that our framework significantly improves code quality, achieving nearly a 3.4× enhancement over prior methods. In the best-case scenario, functional pass rates of 77% for Verilog and 66% for VHDL were obtained, thus substantially improving the reliability of LLM-driven RTL code generation. © 2024, CC BY.

关键词： computer debugging

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Timing Analysis Agent: Autonomous Multi-Corner Multi-Mode (MCMM) Timing debugging with Timing Debug Relation Graph

arXiv

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arXiv 2025年

作者： Nainani, Jatin Ho, Chia-Tung Dhurka, Anirudh Ren, Haoxing NVIDIA Research Santa ClaraCA United States NVIDIA Research AustinTX United States

Timing analysis is an essential and demanding verification method for Very Large Scale Integrated (VLSI) circuit design and optimization. In addition, it also serves as the cornerstone of the final sign-off, determining whether the chip is ready to be sent to the semiconductor foundry for fabrication. Recently, as the technology advance relentlessly, smaller metal pitches and the increasing number of devices have led to greater challenges, and longer turn-around-time for experienced human designers to debug timing issues from the Multi-Corner Multi-Mode (MCMM) timing reports. As a result, an efficient and intelligent methodology is highly necessary and essential for debugging timing issues and reduce the turnaround times. Recently, Large Language Models (LLMs) have shown great promise across various tasks in language understanding and interactive decision-making, incorporating reasoning and actions. In this work, we propose a timing analysis agent, that is empowered by multi-LLMs task solving, and incorporates a novel hierarchical planning and solving flow to automate the analysis of timing reports from commercial tool. In addition, we build a Timing Debug Relation Graph (TDRG) that connects the reports with the relationships of debug traces from experienced timing engineers. The timing analysis agent employs the novel Agentic Retrieval Augmented Generation (RAG) approach, that includes agent and coding to retrieve data accurately, on the developed TDRG. In our studies, the proposed timing analysis agent achieves an average 98% pass-rate on a single-report benchmark and a 90% pass-rate for multi-report benchmark from industrial designs, demonstrating its effectiveness and adaptability. © 2025, CC BY.

关键词： computer debugging

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Gensors: Authoring Personalized Visual Sensors with Multimodal Foundation Models and Reasoning

arXiv

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arXiv 2025年

作者： Liu, Michael Xieyang Petridis, Savvas Tsai, Vivian Fiannaca, Alexander J. Olwal, Alex Terry, Michael Cai, Carrie J. Google DeepMind PittsburghPA United States Google DeepMind New YorkNY United States Google DeepMind Mountain ViewCA United States Google DeepMind SeattleWA United States Google Research Mountain ViewCA United States Google DeepMind CambridgeMA United States

Multimodal large language models (MLLMs), with their expansive world knowledge and reasoning capabilities, present a unique opportunity for end-users to create personalized AI sensors capable of reasoning about complex situations. A user could describe a desired sensing task in natural language (e.g., "let me know if my toddler is getting into mischief in the living room"), with the MLLM analyzing the camera feed and responding within just seconds. In a formative study, we found that users saw substantial value in defining their own sensors, yet struggled to articulate their unique personal requirements to the model and debug the sensors through prompting alone. To address these challenges, we developed Gensors, a system that empowers users to define customized sensors supported by the reasoning capabilities of MLLMs. Gensors 1) assists users in eliciting requirements through both automatically-generated and manually created sensor criteria, 2) facilitates debugging by allowing users to isolate and test individual criteria in parallel, 3) suggests additional criteria based on user-provided images, and 4) proposes test cases to help users "stress test" sensors on potentially unforeseen scenarios. In a 12-participant user study, users reported significantly greater sense of control, understanding, and ease of communication when defining sensors using Gensors. Beyond addressing model limitations, Gensors supported users in debugging, eliciting requirements, and expressing unique personal requirements to the sensor through criteria-based reasoning;it also helped uncover users’ own "blind spots" by exposing overlooked criteria and revealing unanticipated failure modes. Finally, we describe insights into how unique characteristics of MLLMs–such as hallucinations and inconsistent responses–can impact the sensor-creation process. Together, these findings contribute to the design of future MLLM-powered sensing systems that are intuitive and customizable by everyday users. ©

关键词： computer debugging

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Adding data provenance support to Apache Spark

Adding data provenance support to Apache Spark

引用

VLDB Journal

作者： Interlandi, Matteo Ekmekji, Ari Shah, Kshitij Gulzar, Muhammad Ali Tetali, Sai Deep Kim, Miryung Millstein, Todd Condie, Tyson Microsoft RedmondWA United States University of California Los Angeles Los AngelesCA United States Stanford University StanfordCA United States

debugging data processing logic in data-intensive scalable computing (DISC) systems is a difficult and time-consuming effort. Today’s DISC systems offer very little tooling for debugging programs, and as a result, programmers spend countless hours collecting evidence (e.g., from log files) and performing trial-and-error debugging. To aid this effort, we built Titian, a library that enables data provenance—tracking data through transformations—in Apache Spark. Data scientists using the Titian Spark extension will be able to quickly identify the input data at the root cause of a potential bug or outlier result. Titian is built directly into the Spark platform and offers data provenance support at interactive speeds—orders of magnitude faster than alternative solutions—while minimally impacting Spark job performance; observed overheads for capturing data lineage rarely exceed 30% above the baseline job execution time. © 2017, Springer-Verlag GmbH Germany.

关键词： Data handling Computation theory computer debugging Electric sparks Program debugging Alternative solutions Capturing data Data provenance Job performance Orders of magnitude Scalable computing Spark platforms Trial and error

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Using Efficient Path Profiling to optimize memory consumption of on-chip debugging for High-Level Synthesis

Using Efficient Path Profiling to optimize memory consumptio...

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ACM Transactions on Embedded Computing Systems

作者： Fezzardi, Pietro Lattuada, Marco Ferrandi, Fabrizio Politecnico diMilano Italy

High-Level Synthesis (HLS) for FPGAs is attracting popularity and is increasingly used to handle complex systems with multiple integrated components. To increase performance and efficiency, HLS flows now adopt several advanced optimization techniques. Aggressive optimizations and system level integration can cause the introduction of bugs that are only observable on-chip. debugging support for circuits generated with HLS is receiving a considerable attention. Among the data that can be collected on chip for debugging, one of the most important is the state of the Finite State Machines (FSM) controlling the components of the circuit. However, this usually requires a large amount of memory to trace the behavior during the execution. This work proposes an approach that takes advantage of the HLS information and of the structure of the FSM to compress control flow traces and to integrate optimized components for on-chip debugging. The generated checkers analyze the FSM execution on-fly, automatically notifying when a bug is detected, localizing it and providing data about its cause. The traces are compressed using a software profiling technique, called Efficient Path Profiling (EPP), adapted for the debugging of hardware accelerators generated with HLS. With this technique, the size of the memory used to store control flow traces can be reduced up to 2 orders of magnitude, compared to state-of-the-art. © 2017 ACM.

关键词： High level synthesis computer debugging Program debugging Bug detection Efficient path Hardware accelerators Integrated components Memory optimization On chip debugging Optimization techniques System level integration

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